Method and circuit for transmitting a memory clock signal
DCFirst Claim
1. A method for transmitting clock signals, the method comprising:
- receiving, at a memory device, a first clock signal and a second clock signal, wherein a frequency of the first clock signal is less than a frequency of the second clock signal;
performing two or more data access operations using the second clock signal, wherein at least one of the two or more data access operations includes a read operation and wherein at least one of the two or more data access operations includes a write operation; and
performing a command processing operation using the first clock signal.
5 Assignments
Litigations
1 Petition
Accused Products
Abstract
Embodiments of the invention generally provide a method and apparatus for transmitting and receiving clock signals. In one embodiment, the method includes receiving, at a memory device, a first clock signal and a second clock signal. The frequency of the first clock signal may be less than the frequency of the second clock signal. The method further includes performing two or more data access operations using the second clock signal. One of the two or more data access operations may include a read operation and one of the two or more data access operations may include a write operation. The method also includes performing a command processing operation using the first clock signal.
10 Citations
28 Claims
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1. A method for transmitting clock signals, the method comprising:
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receiving, at a memory device, a first clock signal and a second clock signal, wherein a frequency of the first clock signal is less than a frequency of the second clock signal; performing two or more data access operations using the second clock signal, wherein at least one of the two or more data access operations includes a read operation and wherein at least one of the two or more data access operations includes a write operation; and performing a command processing operation using the first clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for providing clock signals to a memory device, the method comprising:
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providing, to the memory device, a first clock signal and a second clock signal, wherein a frequency of the first clock signal is less than a frequency of the second clock signal; providing command data to the memory device using the first clock signal; performing a read operation from the memory device using the second clock signal; and performing a write operation to the memory device using the second clock signal. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A memory device comprising:
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a memory array; an interface to a control device; and circuitry configured to; receive a first clock signal and a second clock signal via the interface, wherein a frequency of the first clock signal is less than a frequency of the second clock signal; perform two or more data access operations using the second clock signal, wherein at least one of the two or more data access operations includes a read operation wherein data is read from the memory array and wherein at least one of the two or more data access operations includes a write operation where data is written to the memory array; and perform a command processing operation using the first clock signal. - View Dependent Claims (17, 18, 19)
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20. A device comprising:
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an interface to a memory device; and circuitry configured to; provide, to the memory device, a first clock signal and a second clock signal via the interface, wherein a frequency of the first clock signal is less than a frequency of the second clock signal; provide command data to the memory device using the first clock signal; perform a read operation from the memory device using the second clock signal; and perform a write operation to the memory device using the second clock signal. - View Dependent Claims (21, 22, 23)
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24. A memory device comprising:
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means for storing data; means for interfacing a control device; and circuitry configured to; receive a first clock signal and a second clock signal via the means for interfacing, wherein a frequency of the first clock signal is less than a frequency of the second clock signal; perform two or more data access operations using the second clock signal, wherein at least one of the two or more data access operations includes a read operation wherein data is read from the means for storing data and wherein at least one of the two or more data access operations includes a write operation where data is written to the means for storing data; and perform a command processing operation using the first clock signal. - View Dependent Claims (25, 26, 27)
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28. A system comprising:
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a memory device; and a control device configured to; provide, to the memory device, a first clock signal and a second clock signal via the interface, wherein a frequency of the first clock signal is less than a frequency of the second clock signal; provide command data to the memory device using the first clock signal; perform a read operation from the memory device using the second clock signal, wherein the memory device is configured to process a read command for the read operation using the first clock signal and to provide a read clock signal generated from the second clock signal to the control device during transmission of read data for the read operation; and perform a write operation to the memory device using the second clock signal, wherein the memory device is configured to process a write command for the write operation using the first clock signal.
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Specification