Scheme for erasure locator polynomial calculation in error-and-erasure decoder
First Claim
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1. A method to generate an erasure locator polynomial in an error-and-erasure decoder, comprising the steps of:
- (A) storing a plurality of current values in a plurality of registers;
(B) generating a plurality of first values by multiplying each one of said current values by a respective one of a plurality of constants;
(C) generating a plurality of second values by gating at least all but one of said first values with a current one of a plurality of erasure values of an erasure location vector;
(D) generating a plurality of next values by combining each one of said second values with a corresponding one of said first values;
(E) loading said next values into said registers in place of said current values; and
(F) generating an output signal carrying said current values such that said current values form a plurality of coefficients of said erasure locator polynomial.
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Abstract
A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial.
17 Citations
18 Claims
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1. A method to generate an erasure locator polynomial in an error-and-erasure decoder, comprising the steps of:
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(A) storing a plurality of current values in a plurality of registers; (B) generating a plurality of first values by multiplying each one of said current values by a respective one of a plurality of constants; (C) generating a plurality of second values by gating at least all but one of said first values with a current one of a plurality of erasure values of an erasure location vector; (D) generating a plurality of next values by combining each one of said second values with a corresponding one of said first values; (E) loading said next values into said registers in place of said current values; and (F) generating an output signal carrying said current values such that said current values form a plurality of coefficients of said erasure locator polynomial. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A circuit comprising:
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a plurality of registers (i) storing a plurality of current values and (ii) generating an output signal carrying said current values such that said current values form a plurality of coefficients of an erasure locator polynomial in an error-and-erasure decoder; a plurality of multiplier modules generating a plurality of first values by multiplying each one of said current values by a respective one of a plurality of constants; a plurality of first modules generating a plurality of second values by gating at least all but one of said first values with a current one of plurality of erasure elements of an erasure location vector; and a plurality of summing modules (i) generating a plurality of next values by combining each one of said second values with a corresponding one of said first values and (ii) loading said next values into said registers in place of said current values. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A system comprising:
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a first circuit configured to generate an erasure locator polynomial in response to all of (a) an erasure location vector and (b) a plurality of constants, wherein each of said constants is a multiplication factor in a respective one of a plurality of multiplier modules; a second circuit configured to generate a plurality of syndromes in response to an input codeword; and a third circuit configured to generate an output signal carrying a reconstructed codeword in response to all of (i) said erasure locator polynomial, (ii) said syndromes and (iii) said input codeword, wherein (a) said first circuit comprises a plurality of registers configured to (i) store a plurality of current values and (ii) generate an intermediate signal carrying said current values such that said current values form a plurality of coefficients of said erasure locator polynomial, (b) said multiplier modules are configured to generate a plurality of first values by multiplying said current values by said respective constants and (c) said first circuit further comprises a plurality of first modules configured to generate a plurality of second values by gating at least all but one of said first values with a current one of plurality of erasure values of said erasure location vector. - View Dependent Claims (17, 18)
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Specification
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Current AssigneeAvago Technologies General IP PTE Limited (Broadcom, Inc.)
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Original AssigneeLSI Corporation (Broadcom, Inc.)
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InventorsPanteleev, Pavel A., Gasanov, Elyar E., Andreev, Alexander, Neznanov, Ilya V., Aliseychik, Pavel A.
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Primary Examiner(s)MCCARTHY, CHRISTOPHER S
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Application NumberUS12/182,443Publication NumberTime in Patent Office1,532 DaysField of SearchNoneUS Class Current714/781CPC Class CodesH03M 13/1515 Reed-Solomon codesH03M 13/153 using the Berlekamp-Massey ...H03M 13/1535 using the Euclid algorithmH03M 13/154 Error and erasure correctio...H03M 13/1545 Determination of error loca...H03M 13/159 Remainder calculation, e.g....
