Semiconductor device and method for fabricating the same

US 8,354,726 B2
Filed: 05/15/2007
Issued: 01/15/2013
Est. Priority Date: 05/19/2006
Status: Active Grant

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1. A semiconductor device comprising:

a first active region surrounded with an isolation region of a semiconductor substrate;

a first gate electrode formed over the first active region and having a protrusion protruding on the isolation region;

a first side-wall insulating film formed on the side surface of the first gate electrode;

an auxiliary pattern formed over the semiconductor substrate to be spaced apart in the gate width direction from the protrusion of the first gate electrode;

a second side-wall insulating film formed on the side surface of the auxiliary pattern; and

a stress-containing insulating film containing internal stress and formed to cover the first gate electrode, the first side-wall insulating film, the auxiliary pattern, and the second side-wall insulating film,wherein the distance between the first gate electrode and the auxiliary pattern is smaller than the sum total of;

the sum of the thicknesses of the first and second side-wall insulating films; and

the double of the thickness of the stress-containing insulating film,the first side-wall insulating film includes a first sidewall formed on the side surface of the first gate electrode, and having an L-shaped cross section, and a second sidewall formed on the first sidewall,the first sidewall is made of an oxide film, andthe second sidewall is made of a nitride film.

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Abstract

A semiconductor device includes: a first active region surrounded with an isolation region of a semiconductor substrate; a first gate electrode formed over the first active region and having a protrusion protruding on the isolation region; a first side-wall insulating film; an auxiliary pattern formed to be spaced apart in the gate width direction from the protrusion of the first gate electrode; a second side-wall insulating film; and a stress-containing insulating film containing internal stress and formed to cover the first gate electrode, the first side-wall insulating film, the auxiliary pattern, and the second side-wall insulating film. In this device, the distance between the first gate electrode and the auxiliary pattern is smaller than the sum total of: the sum of the thicknesses of the first and second side-wall insulating films; and the double of the thickness of the stress-containing insulating film.

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64 Claims

1. A semiconductor device comprising:
- a first active region surrounded with an isolation region of a semiconductor substrate;
  
  a first gate electrode formed over the first active region and having a protrusion protruding on the isolation region;
  
  a first side-wall insulating film formed on the side surface of the first gate electrode;
  
  an auxiliary pattern formed over the semiconductor substrate to be spaced apart in the gate width direction from the protrusion of the first gate electrode;
  
  a second side-wall insulating film formed on the side surface of the auxiliary pattern; and
  
  a stress-containing insulating film containing internal stress and formed to cover the first gate electrode, the first side-wall insulating film, the auxiliary pattern, and the second side-wall insulating film,wherein the distance between the first gate electrode and the auxiliary pattern is smaller than the sum total of;
  
  the sum of the thicknesses of the first and second side-wall insulating films; and
  
  the double of the thickness of the stress-containing insulating film,the first side-wall insulating film includes a first sidewall formed on the side surface of the first gate electrode, and having an L-shaped cross section, and a second sidewall formed on the first sidewall,the first sidewall is made of an oxide film, andthe second sidewall is made of a nitride film.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
- - 2. The device of claim 1, wherein a portion of the stress-containing insulating film formed in an area between the first gate electrode and the auxiliary pattern has a greater thickness than a portion of the stress-containing insulating film formed on the isolation region spaced apart in the gate length direction from the first side-wall insulating film.
  - 3. The device of claim 1, wherein the top surface of a portion of the stress-containing insulating film formed in an area between the first gate electrode and the auxiliary pattern has an equal level to or a higher level than the top surface of the first gate electrode.
  - 4. The device of claim 1, wherein the space between the first gate electrode and the auxiliary pattern is filled with the first and second side-wall insulating films and the stress-containing insulating film.
  - 5. The device of claim 1, wherein the space between the first gate electrode and the auxiliary pattern is filled with the first and second side-wall insulating films.
  - 6. The device of claim 1, wherein the distance between the first gate electrode and the auxiliary pattern is smaller than the sum of the thicknesses of parts of the first side-wall insulating film formed on the side surface of the first gate electrode parallel to the gate width direction and parts of the second side-wall insulating film formed on the side surface of the auxiliary pattern parallel to the gate width direction.
  - 7. The device of claim 1, wherein each of the second sidewalls contains internal stress.
  - 8. The device of claim 1, wherein the auxiliary pattern is a second gate electrode which is formed over a second active region surrounded with the isolation region of the semiconductor substrate and which has a protrusion protruding on the isolation region.
  - 9. The device of claim 8, whereinthe first active region and the first gate electrode are provided in a field effect transistor which is an n-type MIS transistor, andthe second active region and the second gate electrode are provided in a field effect transistor which is a p-type MIS transistor.
  - 10. The device of claim 8, wherein the side surfaces of the first and second gate electrodes located in the gate length direction face each other.
  - 11. The device of claim 8, wherein the side surfaces of the first and second gate electrodes are shifted in the gate length direction with each other.
  - 12. The device of claim 11, wherein a shift distance of the second gate electrode with respect to the first gate electrode is included within a range in which a part of the stress-containing insulating film formed on the side surface of the first gate electrode and a part of the stress-containing insulating film formed on the side surface of the second gate electrode partially overlap with each other in a gate length direction.
  - 13. The device of claim 11, whereina shift distance of the second gate electrode with respect to the first gate electrode is 0 μ
    - m or more and less than a predetermined value,the predetermined value is a sum of;
      
      a sum of a gate length of the first gate electrode and a total thickness of the first side-wall insulating film and a part of the stress-containing insulating film formed on the side surface of the first gate electrode; and
      
      a total thickness of the second side-wall insulating film and a part of the stress-containing insulating film formed on the side surface of the second gate electrode.
  - 14. The device of claim 1, wherein the auxiliary pattern is formed only on the isolation region.
  - 15. The device of claim 1, wherein the auxiliary pattern does not effectively perform electrical operations.
  - 16. The device of claim 1, wherein the auxiliary pattern is made of a different material from that of the first gate electrode.
  - 17. The device of claim 1, wherein the isolation region is formed from an STI (shallow trench isolation) made by filling a trench formed in the semiconductor substrate with an insulating film.
  - 18. The device of claim 1, wherein the stress-containing insulating film is a silicon nitride film.
  - 19. The device of claim 1, whereinthe first gate electrode is made of polysilicon, andthe first gate electrode includes a silicide layer including a nickel.
  - 20. The device of claim 1, wherein the first gate electrode is formed on the first active region through a gate insulating film including nitrogen.
  - 21. The device of claim 1, whereinthe first gate electrode is formed on the first active region through a gate insulating film, andthe gate insulating film is made of SiO₂, SiON or HfSiON.
  - 22. The device of claim 1, wherein the first side-wall insulating film further includes an offset spacer having a plate-like cross section.
  - 23. The device of claim 1, further comprisinga source region or a drain region formed in a region located outside the first side-wall insulating film in the first active region,a silicide layer formed on the source region or the drain region,an interlayer insulating film on the silicide layer through the stress-containing insulating film, anda contact plug passing through the interlayer insulating film and the stress-containing insulating film to reach the silicide layer,wherein the contact plug includes tungsten.
  - 24. The device of claim 23, wherein the silicide layer includes nickel.
  - 25. The device of claim 1, wherein the first side-wall insulating film and the second side-wall insulating film are in contact with each other in a region between the first gate electrode and the auxiliary pattern.
  - 26. The device of claim 1, wherein the first active region and the first gate electrode are provided in a field effect transistor which is an n-type MIS transistor.
  - 27. The device of claim 1, wherein the stress-containing insulating film generates a tensile stress in a channel length direction in the first active region.
  - 28. The device of claim 1, wherein a minimum distance between the first side-wall insulating film and the second side-wall insulating film is less than twice a thickness of a part of the stress-containing insulating film on the first gate electrode, the distance being formed between the first gate electrode and the auxiliary pattern.

29. A semiconductor device comprising:
- a first active region surrounded with an isolation region of a semiconductor substrate;
  
  a first gate electrode formed over the first active region and having a protrusion protruding on the isolation region;
  
  a first side-wall insulating film formed on the side surface of the first gate electrode;
  
  an auxiliary pattern formed over the semiconductor substrate to be spaced apart in the gate width direction from the protrusion of the first gate electrode;
  
  a second side-wall insulating film formed on the side surface of the auxiliary pattern; and
  
  a stress-containing insulating film containing internal stress and formed to cover the first gate electrode, the first side-wall insulating film, the auxiliary pattern, and the second side-wall insulating film,wherein the distance between the first gate electrode and the auxiliary pattern is smaller than the sum total of;
  
  the sum of the thicknesses of the first and second side-wall insulating films; and
  
  the double of the thickness of the stress-containing insulating film, andthe first side-wall insulating film and the second side-wall insulating film are in contact with each other in a region between the first gate electrode and the auxiliary pattern.
- View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
- - 30. The device of claim 29, wherein a portion of the stress-containing insulating film formed in an area between the first gate electrode and the auxiliary pattern has a greater thickness than a portion of the stress-containing insulating film formed on the isolation region spaced apart in the gate length direction from the first side-wall insulating film.
  - 31. The device of claim 29, wherein the space between the first gate electrode and the auxiliary pattern is filled with the first and second side-wall insulating films and the stress-containing insulating film.
  - 32. The device of claim 29, wherein the distance between the first gate electrode and the auxiliary pattern is smaller than the sum of the thicknesses of parts of the first side-wall insulating film formed on the side surface of the first gate electrode parallel to the gate width direction and parts of the second side-wall insulating film formed on the side surface of the auxiliary pattern parallel to the gate width direction.
  - 33. The device of claim 29, wherein each of the first and second side-wall insulating films includes a first sidewall with an L-shaped cross section.
  - 34. The device of claim 29, wherein the auxiliary pattern is a second gate electrode which is formed over a second active region surrounded with the isolation region of the semiconductor substrate and which has a protrusion protruding on the isolation region.
  - 35. The device of claim 34, wherein the side surfaces of the first and second gate electrodes located in the gate length direction face each other.
  - 36. The device of claim 34, wherein the side surfaces of the first and second gate electrodes are shifted in the gate length direction with each other.
  - 37. The device of claim 36, wherein a shift distance of the second gate electrode with respect to the first gate electrode is included within a range in which a part of the stress-containing insulating film formed on the side surface of the first gate electrode and a part of the stress-containing insulating film formed on the side surface of the second gate electrode partially overlap with each other in a gate length direction.
  - 38. The device of claim 36, whereina shift distance of the second gate electrode with respect to the first gate electrode is 0 μ
    - m or more and less than a predetermined value,the predetermined value is a sum of;
      
      a sum of a gate length of the first gate electrode and a total thickness of the first side-wall insulating film and a part of the stress-containing insulating film formed on the side surface of the first gate electrode; and
      
      a total thickness of the second side-wall insulating film and a part of the stress-containing insulating film formed on the side surface of the second gate electrode.
  - 39. The device of claim 29, wherein the stress-containing insulating film is a silicon nitride film.
  - 40. The device of claim 29, whereinthe first gate electrode is made of polysilicon, andthe first gate electrode includes a silicide layer including a nickel.
  - 41. The device of claim 29, wherein the first gate electrode is formed on the first active region through a gate insulating film including nitrogen.
  - 42. The device of claim 29, further comprisinga source region or a drain region formed in a region located outside the first side-wall insulating film in the first active region,a silicide layer formed on the source region or the drain region,an interlayer insulating film on the silicide layer through the stress-containing insulating film, anda contact plug passing through the interlayer insulating film and the stress-containing insulating film to reach the silicide layer,wherein the contact plug includes tungsten, andthe silicide layer includes nickel.

43. A semiconductor device comprising:
- a first active region surrounded with an isolation region of a semiconductor substrate;
  
  a first gate electrode formed over the first active region and having a protrusion protruding on the isolation region;
  
  a first side-wall insulating film formed on the side surface of the first gate electrode;
  
  a second active region surrounded with the isolation region of the semiconductor substrate;
  
  a second gate electrode formed over the second active region, having a protrusion protruding on the isolation region, and formed over the semiconductor substrate to be spaced apart in the gate width direction from the protrusion of the first gate electrode;
  
  a second side-wall insulating film formed on the side surface of the second gate electrode; and
  
  a silicon nitride film formed to cover the first gate electrode, the first side-wall insulating film, the second gate electrode, and the second side-wall insulating film,wherein the distance between the first gate electrode and the second gate electrode is smaller than the sum total of;
  
  the sum of the thicknesses of the first and second side-wall insulating films; and
  
  the double of the thickness of the silicon nitride film,the side surfaces of the first and second gate electrodes are shifted in the gate length direction with each other,a shift distance of the second gate electrode with respect to the first gate electrode is 0 μ
  
  m or more and less than a predetermined value,the predetermined value is a sum of;
  
  a sum of a gate length of the first gate electrode and a total thickness of the first side-wall insulating film and a part of the silicon nitride film formed on the side surface of the first gate electrode; and
  
  a total thickness of the second side-wall insulating film and a part of the silicon nitride film formed on the side surface of the second gate electrode.
- View Dependent Claims (44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64)
- - 44. The device of claim 43, wherein a portion of the silicon nitride film formed in an area between the first gate electrode and the second gate electrode has a greater thickness than a portion of the silicon nitride film formed on the isolation region spaced apart in the gate length direction from the first side-wall insulating film.
  - 45. The device of claim 43, wherein the top surface of a portion of the silicon nitride film formed in an area between the first gate electrode and the second gate electrode has an equal level to or a higher level than the top surface of the first gate electrode.
  - 46. The device of claim 43, wherein the space between the first gate electrode and the second gate electrode is filled with the first and second side-wall insulating films and the silicon nitride film.
  - 47. The device of claim 43, wherein the space between the first gate electrode and the second gate electrode is filled with the first and second side-wall insulating films.
  - 48. The device of claim 43, wherein the distance between the first gate electrode and the second gate electrode is smaller than the sum of the thicknesses of parts of the first side-wall insulating film formed on the side surface of the first gate electrode parallel to the gate width direction and parts of the second side-wall insulating film formed on the side surface of the second gate electrode parallel to the gate width direction.
  - 49. The device of claim 43, wherein each of the first and second side-wall insulating films includes a first sidewall with an L-shaped cross section.
  - 50. The device of claim 49, wherein each of the first and second side-wall insulating films further includes a second sidewall formed to cover an L-shaped inner surface of the first sidewall.
  - 51. The device of claim 50, wherein each of the second sidewalls contains internal stress.
  - 52. The device of claim 43, wherein the isolation region is formed from an STI (shallow trench isolation) made by filling a trench formed in the semiconductor substrate with an insulating film.
  - 53. The device of claim 43, whereinthe first gate electrode is made of polysilicon, andthe first gate electrode includes a silicide layer including a nickel.
  - 54. The device of claim 43, wherein the first gate electrode is formed on the first active region through a gate insulating film including nitrogen.
  - 55. The device of claim 43, whereinthe first gate electrode is formed on the first active region through a gate insulating film, andthe gate insulating film is made of SiO₂, SiON or HfSiON.
  - 56. The device of claim 43, wherein the first side-wall insulating film further includes an offset spacer having a plate-like cross section.
  - 57. The device of claim 43, further comprisinga source region or a drain region formed in a region located outside the first side-wall insulating film in the first active region,a silicide layer formed on the source region or the drain region,an interlayer insulating film on the silicide layer through the silicon nitride film, anda contact plug passing through the interlayer insulating film and the silicon nitride film to reach the silicide layer,wherein the contact plug includes tungsten.
  - 58. The device of claim 57, wherein the silicide layer includes nickel.
  - 59. The device of claim 43, wherein the first active region and the first gate electrode are provided in a field effect transistor which is an n-type MIS transistor.
  - 60. The device of claim 43, wherein the silicon nitride film generates a tensile stress in a channel length direction in the first active region.
  - 61. The device of claim 43, wherein a minimum distance between the first side-wall insulating film and the second side-wall insulating film is less than twice a thickness of a part of the silicon nitride film on the first gate electrode, the distance being formed between the first gate electrode and the second gate electrode.
  - 62. The device of claim 43, whereinthe first active region and the first gate electrode are provided in a field effect transistor which is an n-type MIS transistor, andthe second active region and the second gate electrode are provided in a field effect transistor which is a p-type MIS transistor.
  - 63. The device of claim 43, wherein a shift distance of the second gate electrode with respect to the first gate electrode is included within a range in which a part of the silicon nitride film formed on the side surface of the first gate electrode and a part of the silicon nitride film formed on the side surface of the second gate electrode partially overlap with each other in a gate length direction.
  - 64. The device of claim 43, wherein the silicon nitride film is continuously formed so that the silicon nitride film covers a region from an upper surface of the protrusion of the first gate electrode to an upper surface of a part of the first gate electrode on the first active region.

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Litigation Data

Current Assignee
Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
Original Assignee
Panasonic Corporation (Panasonic Holdings Corporation)
Inventors
Tsutsui, Masafumi
Primary Examiner(s)
Such, Matthew W
Assistant Examiner(s)
Naraghi, Ali

Application Number

US11/798,528
Publication Number

US 20070267707A1
Time in Patent Office

2,072 Days
Field of Search

257288-413, 257/E27.06, 257/E27.062
US Class Current

257/369
CPC Class Codes

H01L 21/823412   with a particular manufactu...

H01L 21/823468   with a particular manufactu...

H01L 21/823481   isolation region manufactur...

H01L 21/823807   with a particular manufactu...

H01L 21/823864   with a particular manufactu...

H01L 21/823878   isolation region manufactur...

H01L 29/665   using self aligned silicida...

H01L 29/6653   using the removal of at lea...

H01L 29/6656   using multiple spacer layer...

H01L 29/6659   with both lightly doped sou...

H01L 29/7842   means for exerting mechanic...

H01L 29/7843   the means being an applied ...

Semiconductor device and method for fabricating the same

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Semiconductor device and method for fabricating the same

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Abstract

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64 Claims

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