Solid state imaging apparatus, method for driving the same and camera using the same
DC- US 8,378,401 B2
- Filed: 12/22/2011
- Issued: 02/19/2013
- Est. Priority Date: 02/13/2003
- Status: Expired due to Term
First Claim
Patent Images
1. A solid state imaging apparatus comprising:
- a plurality of photodiodes arranged in an array;
a plurality of floating diffusion sections each being connected to ones of the plurality of photodiodes via each of a plurality of transfer transistors;
a plurality of read-out lines each being selectively connected to at least two of the plurality of transfer transistors;
a plurality of reset transistors each being connected to one of the plurality of floating diffusion sections;
a plurality of pixel amplifier transistors each detecting and outputting the potential of one of the plurality of floating diffusion sections;
a plurality of signal lines each transferring an output from one of the plurality of pixel amplifier transistors,wherein the plurality of photodiodes include a first photodiode, a second photodiode, a third photodiode and a fourth photodiode,the plurality of transfer transistors include a first transfer transistor, a second transfer transistor, a third transfer transistor and a fourth transfer transistor,the plurality of read-out lines include a first read-out line, a second read-out line, a third read-out line and a fourth read-out line,the first read-out line is adjacent to the second read-out line,the second read-out line is disposed between the first read-out line and the third read-out line,the third read-out line is disposed between the second read-out line and the fourth read-out line,the first read-out line is connected to the first photodiode in row m via the first transfer transistor, where m is a positive integer,the second read-out line is connected to the second photodiode in the row m via the second transfer transistor,the third read-out line is connected to the third photodiode in row m+1 via the third transfer transistor,the fourth read-out line is connected to the fourth photodiode in the row m+1 via the fourth transfer transistors,the first photodiode and the third photodiode are disposed in one of column n and column n+1, where n is a positive integer,the second photodiode and the fourth photodiode are disposed in the other of the column n and the column n+1, andone of the column n and the column n+1 is disposed between one of the plurality of signal lines and the other of the column n and the column n+1.
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Abstract
A solid state imaging apparatus includes: a plurality of photoelectric conversion cells each including a plurality of photoelectric sections arranged in an array of at least two rows and two columns; a plurality of floating diffusion sections each being connected to each of ones of the photoelectric sections which are included in the same row of each said photoelectric conversion cell via each of a plurality of transfer transistors, and being shared by said ones of the photoelectric sections; a plurality of read-out lines each being selectively connected to at least two of the transfer transistors; and a plurality of pixel amplifier transistors each detecting and outputting the potential of each said the floating diffusion section. Charges of the photoelectric conversion sections each being connected to one of the read-out lines and being read out by the transfer transistors are read out by different floating diffusion sections.
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Citations
42 Claims
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1. A solid state imaging apparatus comprising:
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a plurality of photodiodes arranged in an array; a plurality of floating diffusion sections each being connected to ones of the plurality of photodiodes via each of a plurality of transfer transistors; a plurality of read-out lines each being selectively connected to at least two of the plurality of transfer transistors; a plurality of reset transistors each being connected to one of the plurality of floating diffusion sections; a plurality of pixel amplifier transistors each detecting and outputting the potential of one of the plurality of floating diffusion sections; a plurality of signal lines each transferring an output from one of the plurality of pixel amplifier transistors, wherein the plurality of photodiodes include a first photodiode, a second photodiode, a third photodiode and a fourth photodiode, the plurality of transfer transistors include a first transfer transistor, a second transfer transistor, a third transfer transistor and a fourth transfer transistor, the plurality of read-out lines include a first read-out line, a second read-out line, a third read-out line and a fourth read-out line, the first read-out line is adjacent to the second read-out line, the second read-out line is disposed between the first read-out line and the third read-out line, the third read-out line is disposed between the second read-out line and the fourth read-out line, the first read-out line is connected to the first photodiode in row m via the first transfer transistor, where m is a positive integer, the second read-out line is connected to the second photodiode in the row m via the second transfer transistor, the third read-out line is connected to the third photodiode in row m+1 via the third transfer transistor, the fourth read-out line is connected to the fourth photodiode in the row m+1 via the fourth transfer transistors, the first photodiode and the third photodiode are disposed in one of column n and column n+1, where n is a positive integer, the second photodiode and the fourth photodiode are disposed in the other of the column n and the column n+1, and one of the column n and the column n+1 is disposed between one of the plurality of signal lines and the other of the column n and the column n+1. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A solid state imaging apparatus comprising:
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a plurality of photodiodes arranged in an array; a plurality of floating diffusion sections each being connected to ones of the plurality of photodiodes via each of a plurality of transfer transistors; a plurality of read-out lines each being selectively connected to at least two of the plurality of transfer transistors; a plurality of reset transistors each being connected to one of the plurality of floating diffusion sections; a plurality of pixel amplifier transistors each detecting and outputting the potential of one of the plurality of floating diffusion sections; a plurality of signal lines each transferring an output from one of the plurality of pixel amplifier transistors, wherein the plurality of photodiodes include a first photodiode, a second photodiode, a third photodiode and a fourth photodiode, the plurality of transfer transistors include a first transfer transistor, a second transfer transistor, a third transfer transistor and a fourth transfer transistor, the plurality of read-out lines include a first read-out line, a second read-out line, a third read-out line and a fourth read-out line, the first photodiode is in row m and column n, where m and n are a positive integer respectively, the second photodiode is in row m and column n+1, the third photodiode is in row m+1 and column n, the fourth photodiode is in row m+1 and column n+1, the first read-out line is adjacent to the second read-out line, the second read-out line is disposed between the first read-out line and the third read-out line, the third read-out line is disposed between the second read-out line and the fourth read-out line, the first read-out line is connected to the second photodiode via the first transfer transistor, the second read-out line is connected to the first photodiode via the second transfer transistor, the third read-out line is connected to the fourth photodiode via the third transfer transistor, the fourth read-out line is connected to the third photodiode via the fourth transfer transistor, and one of the column n and the column n+1 is disposed between one of the plurality of signal lines and the other of the column n and the column n+1. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A solid state imaging apparatus comprising:
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a plurality of photodiodes arranged in an array; a plurality of floating diffusion sections each being connected to ones of the plurality of photodiodes via each of a plurality of transfer transistors; a plurality of read-out lines each being selectively connected to at least two of the plurality of transfer transistors; a plurality of reset transistors each being connected to one of the plurality of floating diffusion sections; a plurality of pixel amplifier transistors each detecting and outputting the potential of one of the plurality of floating diffusion sections; a plurality of signal lines each transferring an output from one of the plurality of pixel amplifier transistors, wherein the plurality of photodiodes include a first photodiode, a second photodiode, a third photodiode and a fourth photodiode, the plurality of transfer transistors include a first transfer transistor, a second transfer transistor, a third transfer transistor and a fourth transfer transistor, the plurality of read-out lines include a first read-out line, a second read-out line, a third read-out line and a fourth read-out line, the first photodiode is in row m and column n, where m and n are a positive integer respectively, the second photodiode is in row m and column n+1, the third photodiode is in row m+1 and column n, the fourth photodiode is in row m+1 and column n+1, the first read-out line is adjacent to the second read-out line, the second read-out line is disposed between the first read-out line and the third read-out line, the third read-out line is disposed between the second read-out line and the fourth read-out line, the first read-out line is connected to the first photodiode via the first transfer transistor, the second read-out line is connected to the second photodiode via the second transfer transistor, the third read-out line is connected to the third photodiode via the third transfer transistor, the fourth read-out line is connected to the fourth photodiode via the fourth transfer transistor, and one of the column n and the column n+1 is disposed between one of the plurality of signal lines and the other of the column n and the column n+1. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
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Specification
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Litigation Data
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Current AssigneeGodo Kaisha IP Bridge 1 (IP Bridge, Inc.)
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Original AssigneePanasonic Corporation (Panasonic Holdings Corporation)
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InventorsMurata, Takahiko, Mori, Mitsuyoshi, Yamaguchi, Takumi
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Primary Examiner(s)Ingham, John C
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Application NumberUS13/335,537
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Publication Number
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Time in Patent Office425 Days
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Field of Search257/223, 257291-293, 257443-445, 257/E27.132, 257/E27.139
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US Class Current257/292
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CPC Class CodesH01L 27/14609 Pixel-elements with integra...H01L 27/14641 Electronic components share...H04N 25/766 comprising control or outpu...H04N 25/778 comprising amplifiers share...H10F 39/803 Pixels having integrated sw...H10F 39/813 Electronic components share...
