Media converter and a system for mutually converting a packet-based data stream into a serial data stream

US 8,838,822 B2
Filed: 09/20/2006
Issued: 09/16/2014
Est. Priority Date: 09/20/2005
Status: Expired due to Fees

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1. A media converter comprising:

a first interface configured to receive and provide a first type of data stream based on data packets,a second interface configured to receive and provide a second type of data stream based on a continuous serial bit stream,a signal processor, which comprises a transmitter unit including a line encoder, connected to the first and second interfaces and configured to convert said first type of data stream into an output continuous serial bit stream and said second type of data stream into an output data packet data stream on the basis of a block encoding or decoding algorithm and a line encoding or decoding algorithm, whereinsaid signal processor comprises a pad data unit connected to said first interface and configured to add specified symbols to said first type of data stream during silence phases in said first type of data stream, said transmitter unit comprises an idle generator connected to an input of said line encoder, said idle generator being configured to supply a specified idle symbol to the input of said line encoder; and

said signal processor is configured to transmit from the media converter at least said output data packet data stream over an interface other than the second interface.

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Abstract

A media converter, a system and a method for converting packet based data into serial data and vice versa are provided. The media converter comprises a first interface configured to receive and provide a first type of data stream based on data packets, a second interface configured to receive and provide a second type of data stream based on a continuous serial bit stream, and a signal processor connected to the first and second interfaces and configured to convert said first type of data stream into said second type of data stream and vice versa on the basis of a block encoding/decoding algorithm and a line encoding/decoding algorithm. Thus, enhanced bit error rate may be obtained, thereby allowing the use of optical transmission channels of increased length.

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47 Claims

1. A media converter comprising:
- a first interface configured to receive and provide a first type of data stream based on data packets,a second interface configured to receive and provide a second type of data stream based on a continuous serial bit stream,a signal processor, which comprises a transmitter unit including a line encoder, connected to the first and second interfaces and configured to convert said first type of data stream into an output continuous serial bit stream and said second type of data stream into an output data packet data stream on the basis of a block encoding or decoding algorithm and a line encoding or decoding algorithm, whereinsaid signal processor comprises a pad data unit connected to said first interface and configured to add specified symbols to said first type of data stream during silence phases in said first type of data stream, said transmitter unit comprises an idle generator connected to an input of said line encoder, said idle generator being configured to supply a specified idle symbol to the input of said line encoder; and
  
  said signal processor is configured to transmit from the media converter at least said output data packet data stream over an interface other than the second interface.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
- - 2. The media converter of claim 1, wherein said second type of data stream represents a NRZ (non-return to zero) encoded bit stream.
  - 3. The media converter of claim 1, wherein said signal processor comprises a block encoding or decoding section operating on the basis of a forward error correction algorithm.
  - 4. The media converter of claim 1, wherein said signal processor comprises a line encoding or decoding section operating on the basis of an 8 bit or 10 bit conversion algorithm or other n bit or m bit line encoding.
  - 5. The media converter of any of claim 1, wherein said signal processor further comprises a receiver unit including a deserializer, a block decoder and a line decoder and wherein said transmitter unit further comprises a block encoder and a serializer.
  - 6. The media converter of claim 5, wherein said signal processor further comprises a clock generation unit connected to said transmitter unit and said receiver unit.
  - 7. The media converter of claim 5, further comprising a clock input configured to receive an external clock signal for operating said transmitter unit and said receiver unit.
  - 8. The media converter of claim 5, wherein said signal processor further comprises a data recovering unit connected to said second interface to receive a serial bit stream and configured to identify individual bits in said serial bit stream.
  - 9. The media converter of claim 8, wherein said data recovering unit is a digital unit operating on the basis of an over-sampling technique.
  - 10. The media converter of claim 9, wherein said data recovering unit comprises a majority voter mechanism for determining a value of a data bit received via said second interface.
  - 11. The media converter of claim 10, wherein said majority voter mechanism is based on at least three sample time domains.
  - 12. The media converter of claim 11, wherein said data recovering unit comprises a phase locked loop circuit for extracting data bits and a clock signal from said serial bit stream.
  - 13. The media converter of claim 1, wherein said first interface comprises a media independent interface including a transmitter section and a receiver section, said receiver section configured to receive a first continuous clock signal for a nibble based data reception, said transmitter section configured to be operated with a second continuous clock signal for a nibble based data transmission.
  - 14. The media converter of claim 5, wherein said transmitter unit is configured to provide a continuous transmission at an output of said serializer.
  - 15. The media converter of claim 14, wherein said transmitter unit further comprises an output first-in-first out (FIFO) connected between said block encoder and said serializer and wherein said idle generator is further connected to a control output of said output FIFO, and said idle generator supplies said specified idle symbol on the basis of a predefined status of said control output.
  - 16. The media converter of claim 15, wherein said input FIFO is connected to receive symbols from said idle generator.
  - 17. The media converter of claim 16, wherein a symbol width of said input FIFO is selected to provide at least one extra bit for distinguishing data symbols received from said first interface and idle symbols received from said idle generator.
  - 19. The media converter of claim 5, wherein said transmitter unit further comprises an attached synchronization marker (ASM) generator configured to insert one or more predefined synchronization symbols into a data stream provided by said line encoder.
  - 20. The media converter of claim 5, wherein said block encoder comprises a Reed-Solomon encoding scheme or at least one forward error correction technique.
  - 21. The media converter of claim 5, wherein said transmitter unit further comprises an input first-in-first out (FIFO) connected to receive data symbols via said first interface, and an intermediate FIFO connected between said line encoder and said block encoder.
  - 22. The media converter of claim 21, wherein said intermediate FIFO has a capacity of at least the number of check symbols and synchronization symbols generated by the ASM generator and said block encoder.
  - 23. The media converter of claim 5, wherein said block decoder in said receiver unit comprises a Reed-Solomon decoder or other forward error correction decoder.
  - 24. The media converter of claim 5, wherein said deserializer comprises a shift register for parallelizing incoming serial data into symbols having a width corresponding to the input width of said line decoder.
  - 25. The media converter of claim 24, wherein said receiver unit further comprises a block synchronization unit configured to identify an attached synchronization marker symbol and a synchronization state machine for performing a synchronization procedure upon identification of an attached synchronization marker symbol.
  - 30. The media converter of claim 5, wherein said line decoder comprises a control output to indicate whether or not a decoded symbol is a real data symbol.
  - 31. The media converter of claim 30, wherein said receiver unit further comprises packet gap control FIFO connected to receive decoded symbols from said line decoder.
  - 32. The media converter of claim 31, wherein said receiver unit further comprises an output FIFO connected to said packet gap control FIFO and a packet gap control unit.
  - 33. The media converter of claim 32, wherein said packet gap control unit is configured to remove specific non-data symbols included in a group of data symbols forming a data packet and to pass all other symbols prior to storing symbols in said output FIFO.
  - 34. The media converter of claim 33, wherein said packet gap control unit is further configured to remove any non-data symbols except for symbols representing an inter frame gap of said data stream of the first type.
  - 35. The media converter of claim 32, wherein said packet gap control unit is further configured to at least one of add or remove symbols from said output FIFO that represent an inter frame gap of said data stream of the first type for compensating a timing mismatch between the second type of data stream and an operating frequency of the receiver unit.
  - 36. A bi-directional signal conversion system comprising:
    - a media converter according to claim 1, a first physical layer device configured to receive and provide said first type of data stream in the form of electric signals, a second physical layer device configured to receive and provide said second type of data stream in the form of optical signals.
  - 37. The bi-directional signal conversion system of claim 36, wherein said second physical layer device comprises an optical transmitter device and an optical receiver device connected to an optical fibre.
  - 38. The bi-directional signal conversion system of claim 37, wherein said optical fibre comprises a core made of plastic material.
  - 39. The bi-directional signal conversion system of claim 38, wherein said optical receiver device and said optical transmitter device have an operating wavelength in the range of 400 nm to 650 nm.
  - 40. The bi-directional signal conversion system of claim 37, wherein said optical fibre comprises a glass material core.
  - 41. The bi-directional signal conversion system of claim 40, wherein said optical receiver device and said optical transmitter device have an operating wavelength in the range of 800 nm to 1600 nm.

18. The media converter of 17, wherein said line encoder comprises a control input for receiving said at least one extra bit and is configured to encode said data symbols and said symbols on the basis of said received extra bit.

26. The media converter of 25, wherein said synchronization state machine comprises an acquisition state for identifying a predefined number of attached synchronization marker symbols.
- View Dependent Claims (27, 28, 29)
- - 27. The media converter of claim 26, wherein said synchronization state machine further comprises a tracking state for gathering a predefined number of symbols according to an input block length of said block decoder.
  - 28. The media converter of claim 27, wherein said synchronization state machine further comprises an error state detection mechanism that is initiated when no attached synchronization marker symbol is identified after gathering said predefined number of symbols.
  - 29. The media converter of claim 28, wherein said receiver unit further comprises a block FIFO connected between said block synchronization unit and said block decoder for storing said predefined number of symbols received from said block synchronization unit.

42. A method of converting packet based data into serial data and vice versa, the method comprising:
- receiving an incoming packet-based optical data stream over a first interface and converting the incoming packet-based optical data stream into a continuous serial output optical data stream on the basis of line encoding and block encoding,receiving an incoming continuous optical data stream over a second interface and converting the incoming continuous optical data stream into a packet-based output optical data stream on the basis of block decoding and line decoding; and
  
  providing the continuous serial output optical data stream for transmission over the second interface and providing the packet-based output optical data stream for transmission over the first interface.
- View Dependent Claims (43, 44, 45, 46, 47)
- - 43. The method of claim 42, wherein said line encoding comprises providing a specified amount of redundancy for enhancing a bit error rate tolerance.
  - 44. The method of claim 42, wherein said block encoding comprises providing a predefined amount of redundancy for block synchronization and forward error correction.
  - 45. The method of claim 44, wherein said predefined redundancy is 13.8% or more.
  - 46. The method of claim 42, further comprising modulating an interframe gap time of said packet-based output optical data stream so as to compensate for a frequency mismatch between said incoming continuous optical data stream and said line and block decoding.
  - 47. The method of claim 46, wherein modulating of an interframe gap time comprises adding or removing interframe gap symbols from decoded symbols on the basis of a FIFO contents, said FIFO being used for decoding said incoming continuous optical data stream.

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Current Assignee
Optical Measurement Systems, LLC (Equitable IP Corporation)
Original Assignee
Instituto Superiore Mario Boella
Inventors
Nespola, Antonio, Gaudino, Roberto, Spalla, Pietro, Cardenas, Daniel
Primary Examiner(s)
Chao, Michael
Assistant Examiner(s)
MEJIA, FELICIANO S

Application Number

US12/067,284
Publication Number

US 20090024756A1
Time in Patent Office

2,918 Days
Field of Search

709/231, 709/232, 370/536, 370/537, 370/538, 358/440
US Class Current

709/231
CPC Class Codes

H04L 1/0057   Block codes H04L1/0061, H04...

H04L 2007/045   Fill bit or bits, idle words

H04L 25/068   by sampling faster than the...

Media converter and a system for mutually converting a packet-based data stream into a serial data stream

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Abstract

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Media converter and a system for mutually converting a packet-based data stream into a serial data stream

First Claim

5 Assignments

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47 Claims

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