Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing
DCFirst Claim
1. A processor that decodes and executes instructions,the processor comprising:
- a detecting unit for detecting whether an instruction to be decoded is a predetermined instruction; and
a rounding unit for rounding, when the detecting unit is detecting that the instruction is the predetermined instruction, a signed m-bit integer stored at an operand designated by the predetermined instruction to a value expressed as an unsigned s-bit integer wherein s is less than m.
1 Assignment
Litigations
2 Petitions
Accused Products
Abstract
A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.
20 Citations
22 Claims
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1. A processor that decodes and executes instructions,
the processor comprising: -
a detecting unit for detecting whether an instruction to be decoded is a predetermined instruction; and a rounding unit for rounding, when the detecting unit is detecting that the instruction is the predetermined instruction, a signed m-bit integer stored at an operand designated by the predetermined instruction to a value expressed as an unsigned s-bit integer wherein s is less than m. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A processor that decodes and executes instructions,
the processor comprising: -
first detecting unit for detecting whether an instruction to be decoded is an instruction performing a calculation; second detecting unit for detecting whether an instruction to be decoded is an instruction performing both a calculation and a rounding of the calculation result; calculating unit for performing, when the first detecting unit detects that the instruction performs a calculation, a calculation using a signed m-bit integer; and rounding unit for rounding, when the second detecting unit detects the instruction performing both a calculation and a rounding, a result of the calculation performed with a signed m-bit integer to a value expressed as an unsigned s-bit integer wherein s is less than m. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A machine readable medium storing a program that enables a processor for executing a rounding process comprising:
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detection step for directing the processor for detecting whether an instruction to be decoded by the processor is a predetermined instruction; and rounding step for directing the processor for rounding a signed m-bit integer stored at an operand designated by the predetermined instruction to a value expressed as an unsigned s-bit integer wherein s is less than m.
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15. A program recording medium that enables a processor to decode and execute instructions comprising:
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first direction for directing the processor to detect whether an instruction to be decoded is an instruction for performing a calculation; second direction for directing the processor to detect whether an instruction to be decoded is an instruction performing both a calculation and a rounding of the calculation result; third direction for directing the processor to perform, when the processor detects that the instruction performs a calculation, a calculation using a signed m-bit integer; and fourth direction for directing the processor, when the processor is detecting an instruction performing both a calculation and a rounding, for rounding a result of the calculation performed with a signed m-bit integer to a value expressed as an unsigned s-bit integer wherein s is less than m. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A processor that decodes and executes instructions, the processor comprising:
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a detecting unit for detecting whether an instruction to be decoded is a predetermined instruction; and a rounding unit for rounding, when the detecting unit is detecting that the instruction is the predetermined instruction, a signed m-bit integer stored at an operand designated by the predetermined instruction to a value expressed as an unsigned s-bit integer, wherein s is less than m and the rounding of the rounding unit includes the following plural arithmetic operations which are performed within one cycle; (a) testing whether the signed m-bit integer is a negative number or not, (b) testing whether the signed m-bit integer exceeds a predetermined positive number or not, and (c) defining the value expressed as the unsigned s-bit integer in accordance with the testing results of (a) and (b). - View Dependent Claims (22)
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Specification