Hit ahead hierarchical scalable priority encoding logic and circuits
DC CAFC
First Claim
Patent Images
1. A content address able memory(CAM) and hit ahead priority encoding(HAPE) logic, comprising:
- a group of blocks which is arranged in column and row, each block has equal number of CAM match signals which are the input signals of priority encoding logic, each block has same priority encoding logic of CAM match signals within the block, the CAM match signals or input signals are arranged from lower priority to higher priority or from higher priority to lower priority, each CAM match signals or input signal has either high logic level “
one”
which is called hit or low logic level “
zero”
which is called miss, each block generates block hit when there is at least one CAM match signal is high logic “
one”
within the block or block miss signal when all the CAM match signals are in low logic level “
zero”
within the block and block binary address signal corresponding to the CAM match signals of highest priority within the block, a priority encoding logic of block hit or miss signals of each column, each column generates a column hit signal when there is at least one block hit signal within the column or column miss signal when there is only block miss signals within the column and column binary address corresponding to the CAM match signals of highest priority within the column, a priority encoding logic of column hit or miss signals of a group column, a group of column generates a hit signal when there is at least one column hit signal within the group column or a miss signal when there is only column miss signals within the group column and a group column binary address corresponding to the CAM match signals of highest priority within the group column.
0 Assignments
Litigations
0 Petitions
Accused Products
Abstract
In this invention a hit ahead multi-level hierarchical scalable priority encoding logic and circuits are disclosed. The advantage of hierarchical priority encoding is to improve the speed and simplify the circuit implementation and make circuit design flexible and scalable. To reduce the time of waiting for previous level priority encoding result, hit signal is generated first in each level to participate next level priority encoding, and it is called Hit Ahead Priority Encoding (HAPE) encoding. The hierarchical priority encoding can be applied to the scalable architecture among the different sub-blocks and can also be applied with in one sub-block. The priority encoding and hit are processed completely parallel without correlation, and the priority encoding, hit generation, address encoding and MUX selection of the address to next level all share same structure of circuits.
6 Citations
36 Claims
-
1. A content address able memory(CAM) and hit ahead priority encoding(HAPE) logic, comprising:
a group of blocks which is arranged in column and row, each block has equal number of CAM match signals which are the input signals of priority encoding logic, each block has same priority encoding logic of CAM match signals within the block, the CAM match signals or input signals are arranged from lower priority to higher priority or from higher priority to lower priority, each CAM match signals or input signal has either high logic level “
one”
which is called hit or low logic level “
zero”
which is called miss, each block generates block hit when there is at least one CAM match signal is high logic “
one”
within the block or block miss signal when all the CAM match signals are in low logic level “
zero”
within the block and block binary address signal corresponding to the CAM match signals of highest priority within the block, a priority encoding logic of block hit or miss signals of each column, each column generates a column hit signal when there is at least one block hit signal within the column or column miss signal when there is only block miss signals within the column and column binary address corresponding to the CAM match signals of highest priority within the column, a priority encoding logic of column hit or miss signals of a group column, a group of column generates a hit signal when there is at least one column hit signal within the group column or a miss signal when there is only column miss signals within the group column and a group column binary address corresponding to the CAM match signals of highest priority within the group column.- View Dependent Claims (2, 3, 4, 5, 6)
-
7. A content addressable memory (CAM) and hit ahead priority encoding (HAPE) logic, comprising:
-
a group of blocks which are arranged in columns and rows, each block having an equal number of CAM match signals which are the input signals of priority encoding logic, each block having a same priority encoding logic of CAM match signals within the block, the CAM match signals or input signals arranged from lower priority to higher priority or from higher priority to lower priority, each CAM match signal or input signal being either a high logic level “
one which is called hit or a low logic level “
zero”
which is called miss, each block configured to generate a block hit signal when there is at least one CAM match signal that is a high logic level “
one”
within the block or a block miss signal when all the CAM match signals are a low logic level “
zero”
within the block and a block binary address signal corresponding to the CAM match signals of highest priority within the block;a priority encoding logic of block hit or miss signals of each column, each column configured to generate a column hit signal when there is at least one block hit signal within the column or a column miss signal when there are only block miss signals within the column and a column binary address corresponding to the CAM match signals of highest priority within the column; and a priority encoding logic of column hit or miss signals of a group column, the group column configured to generate a hit signal when there is at least one column hit signal within the group column or a miss signal when there are only column miss signals within the group column and a group column binary address corresponding to the CAM match signals of highest priority within the group column. - View Dependent Claims (8, 9, 10, 11, 12)
-
-
13. A content addressable memory (CAM) system, comprising:
-
one or more columns comprising a plurality of circuit segments, at least one of the circuit segments configured to generate a first circuit segment output based on whether at least one of a plurality of circuit segment inputs received by the at least one of the circuit segments corresponds to a first logic level, at least one of the one or more columns configured to generate first address information based on a selected one of the first circuit segment outputs that corresponds to a second logic level, to set a node to a third logic level in response to a first input signal, and to subsequently change the node to a fourth logic level in response to one or more of a plurality of second input signals. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
-
-
29. A content addressable memory (CAM) system, comprising:
-
a circuit segment configured to generate a circuit segment output based on whether at least one of a plurality of circuit segment inputs received by the circuit segment corresponds to a first logic level, the circuit segment configured to set a node to a second logic level in response to an input signal, and to subsequently change the node to a third logic level in response to the plurality of circuit segment inputs, the circuit segment output corresponding to said third logic level. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
Litigation Data
-
Current AssigneeXiaohua Huang
-
Original AssigneeXiaohua Huang
-
InventorsHuang, Xiaohua
-
Primary Examiner(s)Yang, Han
-
Application NumberUS13/355,449Time in Patent Office1,040 DaysField of Search365/49.1, 365/230.01, 365/230.05, 365/230.06US Class Current365/49.1CPC Class CodesG06F 7/74 Selecting or encoding withi...G11C 15/00 Digital stores in which inf...
