Semiconductor device and method for fabricating same
First Claim
Patent Images
1. A semiconductor device, comprising:
- a bare chip fabricated as a large scale integrated circuit, plural bumps provided for an obverse surface of said bare chip, and protective members formed on at least side surfaces of said bare chip.
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Accused Products
Abstract
A top surface of a LSI chip having a structure of a bare chip is provided with bumps, and a protective resin is provided for at least side surfaces of the LSI chips. The LSI chip is prevented from being chipped off or cracked because of protective resin provided for the side surfaces of the LSI chip. The invention provides a semiconductor device and a method for fabricating the same, in which the chip or a package thereof is prevented from being damaged, and thereby yield rate of the semiconductor device can be heightened. Since the numbers of the parts of the semiconductor device and the steps of using jigs and tools necessary for the fabrication process are reduced, fabricating cost of the semiconductor device can be cut down.
43 Citations
22 Claims
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1. A semiconductor device, comprising:
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a bare chip fabricated as a large scale integrated circuit, plural bumps provided for an obverse surface of said bare chip, and protective members formed on at least side surfaces of said bare chip. - View Dependent Claims (2, 3, 4, 5)
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6. A method for fabricating a semiconductor device, comprising the steps of:
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sticking a wafer on which plural bumps are formed to an adhesive sheet, dicing said wafer into individuated chips so as not to dice said adhesive sheet, forming spacings having predetermined widths between said individuated chips stuck to said adhesive sheet, coating said spacings formed between said individuated chips with resin, hardening said resin to unify said individuated chips like a wafer, and providing separate chips by dicing said unified chips along boundary lines between said individuated chips. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
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14. A method for fabricating a semiconductor device, comprising the steps of:
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sticking a wafer on which intermediate electrodes for mounting bumps thereon are arranged in accordance with a circuit pattern to an adhesive sheet, dicing said wafer into individuated chips so as not to dice said adhesive sheet, forming spacings between said individuated chips stuck to said adhesive sheet, coating said spacings formed between said individuated chips and a surface of said wafer on which said intermediated electrodes are arranged with resin, hardening said resin to unify said individuated chips like a wafer, grinding an obverse surface of said unified chips to expose said intermediate electrodes, and providing separate chips by dicing said unified chips along boundary lines between said individuated chips. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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Specification
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Current AssigneeGodo Kaisha IP Bridge 1 (IP Bridge, Inc.)
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Original AssigneeNBC Corp. (West Virginia) (Huntington Bancshares Incorporated)
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InventorsKato, Yoshimasa, Tago, Masamoto
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current438/106
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CPC Class CodesH01L 21/56 Encapsulations, e.g. encaps...H01L 21/561 Batch processingH01L 21/568 Temporary substrate used as...H01L 21/6835 using temporarily an auxili...H01L 21/6836 Wafer tapes, e.g. grinding ...H01L 2221/68327 used during dicing or grindingH01L 2221/68336 involving stretching of the...H01L 2224/023 Redistribution layers [RDL]...H01L 2224/05571 the external layer being di...H01L 2224/05573 Single external layerH01L 2224/05644 Gold [Au] as principal cons...H01L 2224/05647 Copper [Cu] as principal co...H01L 2224/05655 Nickel [Ni] as principal co...H01L 2224/06135 Covering only the periphera...H01L 2224/12105 Bump connectors formed on a...H01L 2224/13099 MaterialH01L 2224/96 the devices being encapsula...H01L 23/3114 the device being a chip sca...H01L 24/05 of an individual bonding areaH01L 24/11 Manufacturing methods for b...View All
