Clock data recovery circuitry associated with programmable logic device circuitry
First Claim
Patent Images
1. Apparatus for receiving and processing a CDR signal comprising:
- PLD circuitry;
first input circuitry configured to receive the CDR signal;
second input circuitry configured to receive a reference clock signal; and
processing circuitry at least partly controlled by the PLD circuitry and configured to use the reference clock signal to recover data information from the CDR signal.
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Abstract
A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.
282 Citations
101 Claims
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1. Apparatus for receiving and processing a CDR signal comprising:
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PLD circuitry;
first input circuitry configured to receive the CDR signal;
second input circuitry configured to receive a reference clock signal; and
processing circuitry at least partly controlled by the PLD circuitry and configured to use the reference clock signal to recover data information from the CDR signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. Apparatus for producing and transmitting a CDR signal comprising:
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PLD circuitry configured to produce data information;
input circuitry configured to receive a reference clock signal; and
output circuitry configured to use the reference clock signal to produce the CDR signal including the data information. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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40. Apparatus for receiving an information signal which includes data information having clock information for the data information embedded in the data information comprising:
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first input circuitry configured to receive the information signal;
second input circuitry configured to receive a reference clock signal having a reference frequency which is related to a frequency of the clock information by a predetermined scale factor;
reference clock signal processing circuitry configured to use the information signal and the reference clock signal to produce a recovered clock signal having phase and frequency which respectively correspond to a phase and a frequency of the clock information; and
data recovery circuitry configured to use the recovered clock signal and the information signal to produce a data output signal indicative of the data information in the information signal. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70)
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71. Apparatus for transmitting an information signal which includes data information having clock information for the data information embedded in the data information comprising:
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input circuitry configured to receive a reference clock signal having a reference frequency which is related to a frequency of the clock information by a predetermined scale factor;
reference clock signal processing circuitry configured to use the reference clock signal to produce a further reference clock signal having the frequency of the clock information;
data source circuitry configured to produce a data signal indicative of the data information; and
data signal processing circuitry configured to process the data signal in accordance with the further reference clock signal to produce the information signal. - View Dependent Claims (72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101)
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Specification