Semiconductor device and method of manufacturing the same
First Claim
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1. A semiconductor device in which a semiconductor element is disposed in each of plural active areas in a semiconductor substrate comprising:
- an isolation for surrounding and isolating each active area, the isolation having a top surface at a higher level than a surface of the active area and having a step portion in a boundary with the active area;
an insulating film formed so as to stretch over each active area and the isolation;
plural holes each formed by removing a portion of the insulating film disposed at least on the active area;
plural buried conductive layers filled in the respective holes; and
plural interconnection members formed on the insulating film so as to be connected with the respective active areas through the respective buried conductive layers.
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Accused Products
Abstract
An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.
5 Citations
38 Claims
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1. A semiconductor device in which a semiconductor element is disposed in each of plural active areas in a semiconductor substrate comprising:
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an isolation for surrounding and isolating each active area, the isolation having a top surface at a higher level than a surface of the active area and having a step portion in a boundary with the active area;
an insulating film formed so as to stretch over each active area and the isolation;
plural holes each formed by removing a portion of the insulating film disposed at least on the active area;
plural buried conductive layers filled in the respective holes; and
plural interconnection members formed on the insulating film so as to be connected with the respective active areas through the respective buried conductive layers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A semiconductor device in which a semiconductor element is disposed in each of plural active areas in a semiconductor substrate comprising:
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a trench isolation for isolating and surrounding each active area, the trench isolation having a top surface at a higher level than a surface of the active area and having a step portion in a boundary with the active area; and
a step sidewall formed on a side surface of the step portion of the trench isolation. - View Dependent Claims (15, 16, 17)
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18. A method of manufacturing a semiconductor device in which a semiconductor element is disposed in each of plural active areas in a semiconductor substrate comprising:
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a first step of forming an isolation in a part of the semiconductor substrate, the isolation having a top surface at a higher level than a surface of the semiconductor substrate and having a step portion in a boundary with the surface of the semiconductor substrate;
a second step of introducing an impurity at a high concentration into each active area of the semiconductor substrate surrounded by the isolation;
a third step of forming an insulating film on the active area and the isolation;
a fourth step of forming, on the insulating film, a masking member having an exposing area above an area at least including a portion of the active area where the impurity at the high concentration is introduced;
a fifth step of conducting etching by using the masking member so as to selectively remove the insulating film and form holes; and
a sixth step of forming a buried conductive layer by filling the holes with a conductive material and forming, on the insulating film, interconnection members to be connected with the buried conductive layer, wherein, in the fourth step, an alignment margin is not provided for preventing the exposing area of the masking member from including a portion above the isolation when mask shift is caused in photolithography. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A method of manufacturing a semiconductor device comprising:
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a first step of forming an underlying insulating film on a semiconductor substrate;
a second step of depositing an etching stopper film on the underlying insulating film;
a third step of forming a trench by exposing a portion of the etching stopper film and the underlying insulating film where an isolation is to be formed and etching the semiconductor substrate in the exposed portion;
a fourth step of depositing an insulating film for isolation on an entire top surface of the substrate, flattening the substrate until at least a surface of the etching stopper film is exposed, and forming a trench isolation in the trench so as to surround a transistor region;
a fifth step of removing, by etching, at least the etching stopper film and the underlying insulating film, so as to expose a step portion between the transistor region and the trench isolation;
a sixth step of depositing a gate oxide film and a conductive film on the substrate and making the conductive film into a pattern of at least a gate electrode;
a seventh step of depositing an insulating film for sidewalls on the entire top surface of the substrate and anisotropically etching the insulating film for the sidewalls, so as to form electrode sidewalls and a step sidewall on side surfaces of the gate electrode and the step portion, respectively; and
an eighth step of introducing an impurity into the semiconductor substrate in the transistor region on both sides of the gate electrode, so as to form source/drain regions. - View Dependent Claims (32, 33, 34)
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35. A method of manufacturing a semiconductor device comprising:
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a first step of forming a gate insulating film on a semiconductor substrate;
a second step of depositing a first conductive film to be formed into a gate electrode on the gate insulating film;
a third step of forming a trench by exposing a portion of the first conductive film where a trench isolation is to be formed and etching the semiconductor substrate in the exposed portion;
a fourth step of depositing an insulating film for isolation on an entire top surface of the substrate, flattening the substrate at least until a surface of the first conductive film is exposed, and forming the trench isolation in the trench so as to surround a transistor region;
a fifth step of depositing a second conductive film to be formed into at least an upper gate electrode on the entire top surface of the flattened substrate;
a sixth step of making the first and second conductive films into a pattern at least of the gate electrode and exposing a step portion between the transistor region and the trench isolation;
a seventh step of depositing an insulating film for sidewalls on the entire top surface of the substrate and anisotropically etching the insulating film for the sidewalls, so as to form electrode sidewalls and a step sidewall on side surfaces of the gate electrode and the step portion, respectively; and
an eighth step of introducing an impurity into the semiconductor substrate in the transistor region on both sides of the gate electrode, so as to form source/drain regions. - View Dependent Claims (36, 37, 38)
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Specification
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Current AssigneeGodo Kaisha IP Bridge 1 (IP Bridge, Inc.)
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Original AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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InventorsYamada, Takayuki, Arai, Masatoshi, Yamashita, Kyoji, Nakabayashi, Takashi, Matsumoto, Michikazu, Miyanaga, Isao, Segawa, Mizuki, Yabu, Toshiki, Uehara, Takashi, Ukeda, Takaaki
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current257/368
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CPC Class CodesH01L 21/76224 using trench refilling with...H01L 29/665 using self aligned silicida...H01L 29/6659 with both lightly doped sou...H01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...
