CLOCK SYNTHESIZER WITH PROGRAMMABLE INPUT-OUTPUT PHASE RELATIONSHIP
First Claim
Patent Images
1. A clock circuit, comprising:
- an oscillator or loop, having a reference input receiving a reference signal, a feedback input receiving a feedback signal, and an output;
a reference path providing said reference signal from a reference clock input; and
a feedback path providing said feedback signal from the oscillator or loop output;
wherein at least one of the reference path and the feedback path comprises a programmable delay circuit.
3 Assignments
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Accused Products
Abstract
A circuit comprising an oscillator, a reference path, and a feedback path. The oscillator may have a reference input receiving a reference signal, a feedback input receiving a feedback signal, and an output. The reference path may provide the reference signal from a reference clock input. The feedback path may provide the feedback signal from the oscillator loop output. At least one of the reference path and the feedback path comprises a programmable delay circuit.
11 Citations
10 Claims
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1. A clock circuit, comprising:
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an oscillator or loop, having a reference input receiving a reference signal, a feedback input receiving a feedback signal, and an output;
a reference path providing said reference signal from a reference clock input; and
a feedback path providing said feedback signal from the oscillator or loop output;
wherein at least one of the reference path and the feedback path comprises a programmable delay circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A circuit comprising:
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means for generating an output in response to (i) a reference input receiving a reference signal and (ii) a feedback input receiving a feedback signal;
means for generating said reference signal from a reference clock input; and
means for generating said feedback signal from the oscillator or loop output, wherein at least one of the reference path and the feedback path comprises a programmable delay circuit.
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9. A method of controlling a clock output, comprising the steps of:
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producing the clock output in response to a reference input and a feedback input; and
delaying at least one of the reference input and the feedback input by a programmable amount of time to thereby control the clock output. - View Dependent Claims (10)
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Specification
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Current AssigneePLL Technologies, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
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Original AssigneeCypress Semiconductor Corporation (Infineon Technologies AG)
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InventorsSEVALIA, PIYUSH, FOX, J. KEN
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current327/105
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CPC Class CodesH03L 2207/10 Indirect frequency synthesi...H03L 7/081 provided with an additional...H03L 7/183 a time difference being use...H03L 7/23 with pulse counters or freq...
