Semiconductor integrated circuit device and method for fabricating the same
First Claim
Patent Images
1. A semiconductor integrated circuit device comprising:
- a circuit pattern having a linear pattern, a perimeter of the linear pattern per unit area being set in a specified range.
2 Assignments
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Accused Products
Abstract
Variations in the size of a linear pattern resulting from difference in mask pattern layout are prevented by setting the perimeter of the linear pattern per unit area in a specified range irrespective of the type of a semiconductor integrated circuit device or by adjusting a process condition in accordance with type-to-type difference in the perimeter of the linear pattern per unit area.
6 Citations
16 Claims
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1. A semiconductor integrated circuit device comprising:
a circuit pattern having a linear pattern, a perimeter of the linear pattern per unit area being set in a specified range.
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2. A semiconductor integrated circuit device comprising:
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a circuit pattern having a linear pattern, a dummy pattern being inserted in a region in which the circuit pattern is placed such that a sum perimeter of the linear pattern and the dummy pattern per unit area is set in a specified range. - View Dependent Claims (3)
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4. A semiconductor integrated circuit device comprising:
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a first circuit pattern having a first linear pattern and placed in a region in which a group of elements having a repetitive pattern are formed; and
a second circuit pattern having a second linear pattern and placed in a region in which components other than the group of elements are formed, a dummy pattern being inserted in the region in which the second circuit pattern is placed such that a sum perimeter of the first linear pattern, the second linear pattern, and the dummy pattern per unit area is equal to or less than a perimeter of the first linear pattern per unit area. - View Dependent Claims (5, 6)
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7. A method for fabricating a plurality of semiconductor integrated circuit devices each comprising a circuit pattern having a linear pattern, at least one of fabrication steps for the semiconductor integrated circuit devices being common, the fabrication steps including the step of:
inserting a dummy pattern in a region in which the circuit pattern is placed such that a sum perimeter of the linear pattern and the dummy pattern per unit area is set in a specified range.
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8. A method for fabricating a semiconductor integrated circuit device, the method comprising the steps of:
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exposing each of a plurality of first regions of a semiconductor substrate to transfer a circuit pattern having a linear pattern onto the first region;
exposing each of a plurality of second regions of the semiconductor substrate other than the first regions to transfer a dummy pattern onto the second region; and
adjusting a ratio between the number of exposing shots for transferring the circuit pattern and the number of exposing shots for transferring the dummy pattern such that a sum perimeter of all the linear patterns transferred and all the dummy patterns transferred per unit area is set in a specified range.
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9. A method for fabricating a plurality of semiconductor integrated circuit devices each comprising a circuit pattern having a linear pattern, at least one of fabrication steps for the semiconductor integrated circuit devices being common, the fabrication steps including the step of:
performing dry etching with respect to a target film while adjusting a dry etching condition in accordance with a perimeter of the linear pattern per unit area. - View Dependent Claims (10)
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11. A method for fabricating a plurality of semiconductor integrated circuit devices each comprising a circuit pattern having a linear pattern, at least one of fabrication steps for the semiconductor integrated circuit devices being common, the fabrication steps including the step of:
forming a resist pattern corresponding to the linear pattern while adjusting a size of the resist pattern in accordance with a perimeter of the linear pattern per unit area. - View Dependent Claims (13, 14, 15, 16)
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12. A method for fabricating a plurality of semiconductor integrated circuit devices each comprising a circuit pattern having a linear pattern, at least one of fabrication steps for the semiconductor integrated circuit devices being common, the fabrication steps including:
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a first step of forming a resist pattern corresponding to the linear pattern on a target film; and
a second step of performing dry etching with respect to the target film by using the resist pattern as a mask, the second step including the step of;
using an etching gas having an effect of protecting a sidewall formed in the target film through the etching or forming an etching reaction product having the sidewall protecting effect, a processing method or a processing condition in at least one of the first and second steps being adjusted in accordance with a ratio between an area occupied by a group of elements contained in the circuit pattern and having a repetitive pattern and an area of a region in which the circuit pattern is placed.
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Specification
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Current AssigneeGodo Kaisha IP Bridge 1 (IP Bridge, Inc.)
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Original AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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InventorsTamaki, Tokuhiko, Kawashima, Koichi, Sakurai, Yasuo, Tateiwa, Kenji
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current438/694
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CPC Class CodesH01L 21/32137 of silicon-containing layersH01L 21/32139 using masks
