Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect
First Claim
1. A method for providing a substantially planar semiconductor topography which extends above a plurality of electrically conductive features that form an integrated circuit, comprising:
- etching a plurality of laterally spaced dummy trenches into a dielectric layer between a relatively wide trench and a series of relatively narrow trenches;
filling said dummy trenches and said wide and narrow trenches with a conductive material;
polishing said conductive material to form dummy conductors exclusively in said dummy trenches and interconnect exclusively in said narrow and wide trenches, wherein said dummy conductors are electrically separate from said plurality of electrically conductive features and co-planar with said interconnect.
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Accused Products
Abstract
The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by forming a plurality of dummy features in a dielectric layer between a relatively wide interconnect and a series of relatively narrow interconnect. According to an embodiment, a plurality of laterally spaced dummy trenches are first etched in the dielectric layer between a relatively wide trench and a series of relatively narrow trenches. The dummy trenches, the wide trench, and the narrow trenches are filled with a conductive material, e.g., a metal. The conductive material is deposited to a level spaced above the upper surface of the dielectric layer. The surface of the conductive material is then polished to a level substantially coplanar with that of the upper surface of the dielectric layer. Advantageously, the polish rate of the conductive material above the dummy trenches and the wide and narrow trenches is substantially uniform. In this manner, dummy conductors spaced apart by dielectric protrusions are formed exclusively in the dummy trenches, and interconnect are formed exclusively in the narrow and wide trenches. The topological surface of the resulting interconnect level is substantially void of surface disparity.
11 Citations
20 Claims
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1. A method for providing a substantially planar semiconductor topography which extends above a plurality of electrically conductive features that form an integrated circuit, comprising:
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etching a plurality of laterally spaced dummy trenches into a dielectric layer between a relatively wide trench and a series of relatively narrow trenches;
filling said dummy trenches and said wide and narrow trenches with a conductive material;
polishing said conductive material to form dummy conductors exclusively in said dummy trenches and interconnect exclusively in said narrow and wide trenches, wherein said dummy conductors are electrically separate from said plurality of electrically conductive features and co-planar with said interconnect. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for providing a semiconductor topography having a plurality of electrically conductive features and a topography which is substantially planar, comprising:
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etching a plurality of laterally spaced dummy trenches into a dielectric layer between a trench which is to receive a relatively wide interconnect feature and a series of trenches which are to receive a relatively narrow interconnect feature;
filling said plurality of dummy trenches with a conductive material; and
polishing said conductive material to form dummy conductors bounded exclusively within said dummy trenches electrically separate from said electrically conductive features, and such that first upper surfaces of said dummy conductors are substantially co-planar with second upper surfaces of said relatively wide and narrow interconnect features. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 18, 19, 20)
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17. A substantially planar semiconductor topography elevationally raised above a plurality of electrically conductive features which receive electrically transitory voltages forwarded through an integrated circuit, comprising:
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a plurality of laterally spaced dummy trenches residing within a dielectric layer between a relatively wide trench and a series of relatively narrow trenches;
dummy conductors bounded exclusively within said dummy trenches and electrically separate from said plurality of electrically conductive features; and
interconnect bounded exclusively within said narrow and wide trenches, wherein interconnect upper surfaces are substantially coplanar with dummy conductor upper surfaces.
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Specification
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- Resources
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Current AssigneeInvensas Corporation
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Original AssigneeCypress Semiconductor Corporation (Infineon Technologies AG)
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InventorsSeams, Christopher A., Sethuraman, Anantha R.
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current438/618
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CPC Class CodesH01L 21/3212 by chemical mechanical poli...
