Architecture for a sea of platforms

US 20030131335A1
Filed: 01/10/2002
Published: 07/10/2003
Est. Priority Date: 01/10/2002
Status: Active Grant

First Claim

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1. A system for providing distributed dynamic functionality in an electronic environment comprising:

a plurality of platforms, the platforms suitable for providing a logic function, the platforms including embedded programmable logic, memory and a reconfigurable core, the logic, memory and reconfigurable core communicatively coupled via a fabric interconnect; and

a map expressing logic functions of the plurality of platforms.

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Abstract

The present invention is directed to platform architecture. A system for providing distributed dynamic functionality in an electronic environment may include a plurality of platforms. The platforms are suitable for providing a logic function, and include embedded programmable logic, memory and a reconfigurable core. The logic, memory and reconfigurable core are communicatively coupled via a fabric interconnect. A map is also included which expresses logic functions of the plurality of platforms.

47 Citations

31 Claims

1. A system for providing distributed dynamic functionality in an electronic environment comprising:
- a plurality of platforms, the platforms suitable for providing a logic function, the platforms including embedded programmable logic, memory and a reconfigurable core, the logic, memory and reconfigurable core communicatively coupled via a fabric interconnect; and
  
  a map expressing logic functions of the plurality of platforms.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- - 2. The system as described in claim 1, wherein the map includes instruction set architecture extensions and embedded programmable logic core adjuncts.
  - 3. The system as described in claim 1, wherein the map describes logic functions as provided by the plurality of platforms on a cycle-by-cycle basis.
  - 4. The system as described in claim 1, wherein the map describes logic functions as provided by the plurality of platforms in a manner so as to express groupings of platforms of the plurality of platforms utilized to perform the logic function.
  - 5. The system as described in claim 1, wherein the embedded programmable logic includes at least one of programmable gate arrays, sea of adders, CPLD structures and programmable circuit elements definable from a stored representation.
  - 6. The system as described in claim 1, wherein the reconfigurable cores are configured as a base processor design plus instruction set extensions designed to carry out function-specific logical and arithmetic operations.
  - 7. The system as described in claim 1, wherein the fabric interconnect is isochronous.
  - 8. The system as described in claim 1, where the fabric interconnect is realized within a switching fabric which permits adaptive interconnect and access paths to be defined on the fly.
  - 9. The system as described in claim 1, wherein the plurality of platforms is communicatively coupled via a fabric interconnect that is isochronous.
  - 10. The system as described in claim 1, wherein instruction set extensions are utilized through the use of the map to coordinate discrete instruction set extensions on a cycle-by-cycle basis and execution is synchronized across the plurality of platforms utilizing an isochronous fabric interconnect so that the instruction set extensions are utilized by corresponding platforms at a corresponding cycle.

11. The system as described in claim 11, wherein logic functions are targeted at the platforms indicated by the map as having corresponding functionality at a corresponding point in time.

12. A method for providing an executable suitable for being employed by a plurality of platforms, comprising:
- receiving a program of instructions;
  
  determining availability of a plurality of platforms for performing the program of instructions, the plurality of platforms including embedded programmable logic, memory and a reconfigurable core, the logic, memory and reconfigurable core communicatively coupled via a fabric interconnect that is isochronous, wherein availability of the platforms includes at least one of load value of the platforms and functionality of the platforms; and
  
  translating the program of instructions into an executable suitable for operation by the plurality of platforms based on the determined availability.
- View Dependent Claims (13, 14, 15, 16, 17)
- - 13. The method as described in claim 12, wherein availability of the platforms is determined by referencing a map.
  - 14. The method as described in claim 13, wherein the map expresses logic functions of the plurality of platforms.
  - 15. The method as described in claim 13, wherein the map includes instruction set architecture extensions and embedded programmable logic core adjuncts.
  - 16. The method as described in claim 13, wherein the map describes logic functions as provided by the plurality of platforms on a cycle-by-cycle basis.
  - 17. The method as described in claim 13, wherein the map describes logic functions as provided by the plurality of platforms in a manner so as to express groupings of platforms of the plurality of platforms utilized to perform the logic function.

18. A system for providing distributed dynamic functionality in an electronic environment comprising:
- a plurality of platforms communicatively coupled via an isochronous fabric, the platforms suitable for providing a logic function, the platforms including embedded programmable logic, memory and a reconfigurable core communicatively coupled; and
  
  a map expressing availability of the plurality of platforms for performing a logic function.
- View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27)
- - 19. The system as described in claim 18, wherein the map includes instruction set architecture extensions and embedded programmable logic core adjuncts.
  - 20. The system as described in claim 18, wherein the map describes logic functions as provided by the plurality of platforms on a cycle-by-cycle basis.
  - 21. The system as described in claim 18, wherein the map describes logic functions as provided by the plurality of platforms in a manner so as to express groupings of platforms of the plurality of platforms utilized to perform the logic function.
  - 22. The system as described in claim 18, wherein the embedded programmable logic includes at least one of programmable gate arrays, sea of adders, CPLD structures and programmable circuit elements definable from a stored representation.
  - 23. The system as described in claim 18, wherein the reconfigurable cores are configured as a base processor design plus instruction set extensions designed to carry out function-specific logical and arithmetic operations.
  - 24. The system as described in claim 18, wherein the fabric interconnect is isochronous.
  - 25. The system as described in claim 18, where the isochronous fabric is realized within a switching fabric which permits adaptive interconnect and access paths to be defined on the fly.
  - 26. The system as described in claim 18, wherein instruction set extensions are utilized through the use of the map to coordinate discrete instruction set extensions on a cycle-by-cycle basis and execution is synchronized across the plurality of platforms utilizing an isochronous fabric interconnect so that the instruction set extensions are utilized by corresponding platforms at a corresponding cycle.
  - 27. The system as described in claim 26, wherein logic functions are targeted at the platforms indicated by the map as having corresponding functionality at a corresponding point in time.

28. A system for providing distributed dynamic functionality in an electronic environment comprising:
- a plurality of platforms communicatively coupled via an isochronous fabric, the platforms suitable for providing a logic function, the platforms including embedded programmable logic, memory and a reconfigurable core communicatively coupled; and
  
  a means for providing a map expressing availability of the plurality of platforms for performing a logic function.
- View Dependent Claims (29, 30, 31)
- - 29. The system as described in claim 28, wherein the map means includes instruction set architecture extensions and embedded programmable logic core adjuncts.
  - 30. The system as described in claim 28, wherein the map means describes logic functions as provided by the plurality of platforms on a cycle-by-cycle basis.
  - 31. The system as described in claim 28, wherein the map means describes logic functions as provided by the plurality of platforms in a manner so as to express groupings of platforms of the plurality of platforms utilized to perform the logic function.

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Current Assignee
Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
Original Assignee
LSI Logic Corporation (Broadcom, Inc.)
Inventors
Hamlin, Christopher L.

Granted Patent

US 6,640,333 B2
Time in Patent Office

Days
Field of Search
US Class Current

716/16
CPC Class Codes

G06F 30/30   Circuit design

G06F 30/34   for reconfigurable circuits...

G06F 30/343   Logical level

Architecture for a sea of platforms

First Claim

10 Assignments

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Abstract

47 Citations

31 Claims

Specification

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Architecture for a sea of platforms

First Claim

10 Assignments

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0 Petitions

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Accused Products

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Abstract

47 Citations

31 Claims

Specification

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Solutions

Use Cases

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