Double-gate FinFET device and fabricating method thereof

US 20040150029A1
Filed: 02/04/2003
Published: 08/05/2004
Est. Priority Date: 02/04/2003
Status: Active Grant

First Claim

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1. A double-gate FinFET device, comprising:

a bulk silicon substrate;

a Fin active region which is a wall-shape single crystalline silicon on a surface of the bulk silicon substrate and connected to said bulk silicon substrate;

a second oxide layer which is formed up to a certain height of the Fin active region from the surface of bulk silicon substrate;

a gate oxide layer which is formed on both side-walls of the Fin active region protruded from said second oxide layer;

a first oxide layer which is formed on the upper surface of said Fin active region with a thickness greater or equal to that of the gate oxide;

a gate which is formed on said first and second oxide layer;

a source/drain region which is formed on both sides of the Fin active region except where said gate overlaps with the Fin active region; and

a contact region and a metal layer which are formed at said source/drain and gate contact region.

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Abstract

The present invention relates to double-gate FinFET devices and fabricating methods thereof. More particularly, the invention relates to an electrically stable double-gate FinFET device and the method of fabrication in which the Fin active region on a bulk silicon substrate where device channel and the body are to be formed has a nano-size width and is connected to the substrate and is formed with the shape of a wall along the channel length direction.

The conventional double-gate MOS devices are fabricated using SOI wafers which are more expensive than bulk silicon wafers. It also has problems including the floating body effects, larger source/drain parasitic resistance, off-current increase, and deterioration in heat transfer to the substrate.

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23 Claims

1. A double-gate FinFET device, comprising:
- a bulk silicon substrate;
  
  a Fin active region which is a wall-shape single crystalline silicon on a surface of the bulk silicon substrate and connected to said bulk silicon substrate;
  
  a second oxide layer which is formed up to a certain height of the Fin active region from the surface of bulk silicon substrate;
  
  a gate oxide layer which is formed on both side-walls of the Fin active region protruded from said second oxide layer;
  
  a first oxide layer which is formed on the upper surface of said Fin active region with a thickness greater or equal to that of the gate oxide;
  
  a gate which is formed on said first and second oxide layer;
  
  a source/drain region which is formed on both sides of the Fin active region except where said gate overlaps with the Fin active region; and
  
  a contact region and a metal layer which are formed at said source/drain and gate contact region.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
- - 2. The device as claimed in claim 1, wherein the width of said Fin active region lies in a range between 4 nm and 100 nm.
  - 3. The device as claimed in claim 1 or claim 2, wherein the height of said Fin active region from the surface of said bulk silicon substrate lies in a range between 10 nm and 1000 nm.
  - 4. The device as claimed in claim 3, wherein the height of said Fin active region from the surface of said second oxide layer is between 5 nm and 300 nm.
  - 5. The device as claimed in claim 1, wherein the thickness of said gate oxide layer is between 0.5 nm and 10 nm, and the thickness of said first oxidation layer is between 0.5 nm and 200 nm.
  - 6. The device as claimed in claim 1, wherein the parasitic capacitance between said gate and bulk silicon substrate is reduced by selecting the thickness of said second oxidation layer to be between 20 nm and 800 nm.
  - 7. The device as claimed in claim 1, wherein the contact resistance is reduced by selecting the size of a contact region which is in contact with said metal layer to be greater than the width of said Fin active region and/or the length of said gate.
  - 8. The device as claimed in claim 1, wherein a selective epitaxial layer is grown on both sides (source/drain region) of the Fin active region except where said Fin active region overlaps with the gate in a self-aligned manner to the gate, in order to reduce parasitic source/drain resistance.
  - 9. The device as claimed in claim 8, wherein said selective epitaxial layer is grown by oxidizing said gate doped with the doping concentration value above 10²⁰cm⁻
    - 3 in wet ambient, and etching some parts of the grown oxide layer using the fact that the gate oxidation rate is greater than the Fin active region, and taking the silicon which is exposed on both side-walls of the Fin active region as a seed.
  - 10. The device as claimed in claim 8, wherein said selective epitaxial layer is grown by depositing a dielectric layer, and anisotropically etching as much as the thickness of the dielectric layer and the height of the Fin active region protruding above the second oxide layer, and taking the silicon which is exposed at side-walls of the Fin active region except the vicinity where the Fin active region and gate meets and a poly-silicon gate, as seeds.
  - 11. The device as in any one of claims 8, 9 or 10, wherein the material for said selective epitaxial layer is selected from the group consisting of a single crystalline silicon, single crystalline SiGe, single crystalline Ge, poly-silicon, and poly SiGe.
  - 12. The device as claimed in claim 1, wherein said doping junction depth for the source/drain form in said Fin active region, when the upper surface of said second oxide layer is taken as a reference level (0 nm), is around 0 nm to 50 nm above the reference level.
  - 13. The device as claimed in claim 1, wherein said doping junction depth for the source/drain form in said Fin active region, when the upper surface of said second oxide layer is taken as a reference level (0 nm), is around 0 nm to −
    - 50 nm below the reference level.
  - 14. The device as claimed in claim 1, wherein the resistance of said Fin active region is reduced by enlarging the width of said Fin active region within the oxidation layer as it approaches the bulk silicon substrate.
  - 15. The device as claimed in claim 1, wherein the shape of said Fin active region is a trapezoid where the width of the upper section is narrow and the lower section is wide.
  - 16. The device as claimed in claim 1, wherein the two top corners of said Fin active region are chamfered through an oxidation and etching, or (and) annealing process in a hydrogen atmosphere.

17. A double-gate FinFET device fabrication method, comprising the steps of:
- forming a wall shape Fin active region which is single crystalline silicon on a bulk silicon substrate;
  
  forming a second oxide layer up to a certain height of the Fin active region from the surface of the bulk silicon substrate;
  
  forming a gate oxide layer at both side-walls of the Fin active region on said second oxide layer;
  
  forming a first oxide layer on the upper surface of said Fin active region with a thickness greater or equal to that of the gate oxide;
  
  forming a gate on said first and second oxide layer;
  
  forming a source/drain region on both sides of the Fin active region except where said gate overlaps with the Fin active region; and
  
  forming a contact region and a metal layer at said source/drain and gate contact region.
- View Dependent Claims (18, 19, 20, 21, 22, 23)
- - 18. The method as claimed in claim 17, wherein said Fin active region and second oxide forming methods further including the steps of;
    - doing photolithography said bulk silicon substrate; and
      
      covering the second oxide layer over the bulk silicon substrate surface and said Fin active region, and planarizing said second oxide layer using Chemical Mechanical Polishing (CMP), and etching the second oxide down to an appropriate thickness from the top surface of said Fin active region.
  - 19. The method as claimed in claim 17, wherein said Fin active region and second oxide forming methods further including the steps of;
    - forming the second oxide layer, and forming a narrow trench on said second oxide layer using a photolithography process where the bottom face of the trench is in contact with the bulk silicon substrate, and growing a selective epitaxial layer by taking the silicon of the bulk silicon substrate, which is exposed at the bottom face of the trench, as a seed; and
      
      etching the second oxide layer by an appropriate thickness.
  - 20. The method as claimed in claim 17, wherein said method of forming said Fin active region further including the steps of doing photolithography said bulk silicon substrate, and forming a first oxide layer/nitride layer/second oxide layer sequentially above the bulk silicon substrate, and etching said first oxide layer/nitride layer/second oxide layer and the silicon of the bulk silicon substrate;
    - and said method of forming the field oxide layer further including the steps of forming a buffer oxide layer/nitride layer/spacer and etching them, and further etching the exposed silicon of the bulk silicon substrate, and growing a field oxide layer by oxidizing the bulk silicon substrate after removing said spacer, and removing the buffer oxide layer and the nitride layer.
  - 21. The method as claimed in claim 20, wherein the material for said spacer is either poly-silicon or amorphous silicon.
  - 22. The method as claimed in claim 17, further including the steps of cleaning the side-walls of the protruding Fin active region before growing said gate oxide layer and carrying out an annealing process in a Nitrogen or Argon atmosphere after removing a sacrificial oxide layer which is grown to remove the damage generated during the previous process.
  - 23. The method as claimed in claim 17, wherein said gate forming method further including the steps of forming a material selected from a group consisting of poly-silicon, poly SiGe, metal, and doing photolithography said layer to define the gate.

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Current Assignee
KIPB LLC (f/k/a KAIST IP US LLC) (P&IB Co. Ltd.)
Original Assignee
Jong Ho Lee
Inventors
Lee, Jong-Ho

Granted Patent

US 6,885,055 B2
Time in Patent Office

Days
Field of Search
US Class Current

257/308
CPC Class Codes

H01L 2029/7858   having contacts specially a...

H01L 29/41791   for transistors with a hori...

H01L 29/66795   with a horizontal current f...

H01L 29/7851   with the body tied to the s...

Double-gate FinFET device and fabricating method thereof

First Claim

6 Assignments

0 Petitions

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Abstract

108 Citations

23 Claims

Specification

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Double-gate FinFET device and fabricating method thereof

First Claim

6 Assignments

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0 Petitions

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Accused Products

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Abstract

108 Citations

23 Claims

Specification

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Solutions

Use Cases

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