Memory controller useable in a data processing system
First Claim
1. A data processing system, comprising:
- a system bus;
a system bus master, coupled to the system bus;
a first memory controller for controlling a first memory;
a second memory controller for controlling a second memory; and
a memory controller bus operating independent of the system bus, said memory controller bus being coupled to the first memory controller and to the second memory controller, said memory controller bus transferring data between the first memory controller and the second memory controller.
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Accused Products
Abstract
One embodiment relates to a memory controller using an independent memory controller bus in order to transfer data between two or more memories. One embodiment of a data processing system includes a system bus, a system bus master coupled to the system bus, a first memory controller for controlling a first memory, a second memory controller for controlling a second memory, and a memory controller bus operating independent of the system bus to transfer data between the first memory controller and the second memory controller. The memory controller bus may include a data bus and read, write, and acknowledge signals. In one embodiment, the first memory is a block accessible memory such as a NAND Flash memory and the second memory is a random access memory (RAM) such as an SDRAM. The second memory may include arbitration logic for arbitrating between the system bus master and the first memory controller.
175 Citations
20 Claims
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1. A data processing system, comprising:
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a system bus;
a system bus master, coupled to the system bus;
a first memory controller for controlling a first memory;
a second memory controller for controlling a second memory; and
a memory controller bus operating independent of the system bus, said memory controller bus being coupled to the first memory controller and to the second memory controller, said memory controller bus transferring data between the first memory controller and the second memory controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 19)
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15. A data processing system, comprising:
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a system bus;
a system bus master, coupled to the system bus;
a first memory controller, coupled to the system bus, for controlling a first memory;
a second memory controller, coupled to the system bus, for controlling a second memory; and
arbitration logic, coupled to the second memory controller, said arbitration logic arbitrating between the system bus master and the first memory controller for access to the second memory. - View Dependent Claims (16, 17, 18)
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20. A data processing system, comprising:
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a system bus;
a processor, coupled to the system bus;
direct memory access (DMA) circuitry coupled to the system bus;
system bus arbitration logic, coupled to the system bus, said system bus arbitration logic performing arbitration on the system bus;
a first memory controller for controlling a first memory;
a second memory controller for controlling a second memory;
a memory controller bus operating independent of the system bus, said memory controller bus being coupled to the first memory controller and to the second memory controller, said memory controller bus transferring data between the first memory controller and the second memory controller; and
memory controller bus arbitration logic, coupled to the memory controller bus, said arbitration logic performing arbitration on the memory controller bus.
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Specification
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- Resources
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Current AssigneeNorth Star Innovations Inc. (Wi-LAN Inc.)
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Original AssigneeFreescale Semiconductor, Inc. (NXP Semiconductors NV)
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InventorsCruz, Arnaldo R.
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current710/22
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CPC Class CodesG06F 13/1605 based on arbitration arbitr...G06F 13/1684 using multiple busesY02D 10/00 Energy efficient computing,...
