Conserving power by reducing voltage supplied to an instruction-processing portion of a processor

US 20050283628A1
Filed: 08/25/2005
Published: 12/22/2005
Est. Priority Date: 04/29/2002
Status: Active Grant

First Claim

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1-20. -20. (canceled)

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Abstract

One embodiment of the present invention provides a system that facilitates reducing static power consumption of a processor. During operation, the system receives a signal indicating that instruction execution within the processor is to be temporarily halted. In response to this signal, the system halts an instruction-processing portion of the processor, and reduces the voltage supplied to the instruction-processing portion of the processor. Full voltage is maintained to a remaining portion of the processor, so that the remaining portion of the processor can continue to operate while the instruction-processing portion of the processor is in reduced power mode.

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42 Claims

1-20. -20. (canceled)

21. A method for reducing static power consumption of a processor, comprising:
- receiving a signal indicating that instruction execution within the processor is to be temporarily halted; and
  
  in response to the signal, halting an instruction-processing portion of the processor, and reducing a voltage supplied to the instruction-processing portion of the processor, thereby reducing power consumption in the processor.
- View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
- - 22. The method of claim 21, wherein reducing a voltage supplied to the instruction-processing portion of the processor further involves maintaining full voltage to a second portion of the processor;
    - whereby the second portion of the processor can continue to operate while the instruction-processing portion of the processor is in a reduced power mode.
  - 23. The method of claim 21, wherein reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to a minimum value that maintains state information within the instruction-processing portion of the processor.
  - 24. The method of claim 21, wherein reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to zero.
  - 25. The method of claim 24, further comprising saving state information from the instruction-processing portion of the processor prior to reducing the voltage supplied to the instruction-processing portion of the processor, wherein saving state information includes saving state information to one of, the second portion of the processor and a main memory.
  - 26. The method of claim 25, wherein upon receiving a wakeup signal the method further comprises:
    - restoring full voltage to the instruction-processing portion of the processor;
      
      restoring state information to the instruction-processing portion of the processor; and
      
      resuming processing of computer instructions.
  - 27. The method of claim 22, wherein maintaining full voltage to the second portion of the processor involves maintaining full voltage to a snoop-logic portion of the processor, whereby the processor can continue to perform cache snooping operations while the instruction-processing portion of the processor is in the reduced power mode.
  - 28. The method of claim 21, further comprising reducing the voltage to a cache memory portion of the processor upon receiving the signal.
  - 29. The method of claim 28, further comprising writing cache memory data to main memory prior to reducing the voltage.
  - 30. The method of claim 21, wherein the second portion of the processor includes a control portion of the processor that includes interrupt and clock circuitry.
  - 31. The method of claim 21, wherein the second portion of the processor includes a cache memory portion of the processor.

32. An apparatus, for reducing static power consumption of a processor, comprising:
- a receiving mechanism that is configured to receive a signal indicating that instruction execution within the processor is to be temporarily halted;
  
  a halting mechanism that is configured to halt an instruction-processing portion of the processor; and
  
  a voltage reducing mechanism that is configured to reduce a voltage supplied to the instruction-processing portion of the processor, thereby reducing power consumption in the processor.
- View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
- - 33. The apparatus of claim 32, wherein while reducing power supplied to the instruction-processing portion of the processor, the voltage reducing mechanism is configured to maintain full voltage to a second portion of the processor;
    - whereby the second portion of the processor can continue to operate while the instruction-processing portion of the processor is in a reduced power mode.
  - 34. The apparatus of claim 32, wherein reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to a minimum value that maintains state information within the instruction-processing portion of the processor.
  - 35. The apparatus of claim 32, wherein reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to zero.
  - 36. The apparatus of claim 35, further comprising a saving mechanism that is configured to save state information from the instruction-processing portion of the processor prior to reducing the voltage supplied to the instruction-processing portion of the processor, wherein saving state information includes saving state information to one of, the second portion of the processor and a main memory.
  - 37. The apparatus of claim 36, further comprising:
    - a voltage restoring mechanism that is configured to restore full voltage to the instruction-processing portion of the processor;
      
      a state restoring mechanism that is configured to restore state information to the instruction-processing portion of the processor; and
      
      a resuming mechanism that is configured to resume processing of computer instructions.
  - 38. The apparatus of claim 33, wherein maintaining full voltage to the second portion of the processor involves maintaining full voltage to a snoop-logic portion of the processor, whereby the processor can continue to perform cache snooping operations while the instruction-processing portion of the processor is in the reduced power mode.
  - 39. The apparatus of claim 32, wherein the voltage reducing mechanism is further configured to reduce the voltage to a cache memory portion of the processor upon receiving the signal.
  - 40. The apparatus of claim 39, further comprising a writing mechanism that is configured to write cache memory data to main memory prior to reducing the voltage.
  - 41. The apparatus of claim 32, wherein the second portion of the processor includes a control portion of the processor that includes interrupt and clock circuitry.
  - 42. The apparatus of claim 32, wherein the second portion of the processor includes a cache memory portion of the processor.

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Current Assignee
Apple Inc.
Original Assignee
Apple Inc.
Inventors
Youngs, Lynn R.

Granted Patent

US 7,383,453 B2
Time in Patent Office

Days
Field of Search
US Class Current

713/300
CPC Class Codes

G06F 1/3203   Power management, i.e. even...

G06F 1/3228   Monitoring task completion,...

G06F 1/3275   Power saving in memory, e.g...

G06F 1/3287   by switching off individual...

G06F 1/3296   by lowering the supply or o...

Y02D 10/00   Energy efficient computing,...

Y02D 30/50   in wire-line communication ...

Conserving power by reducing voltage supplied to an instruction-processing portion of a processor

First Claim

1 Assignment

0 Petitions

Accused Products

Abstract

25 Citations

42 Claims

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Conserving power by reducing voltage supplied to an instruction-processing portion of a processor

First Claim

1 Assignment

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Subscription Required

0 Petitions

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Accused Products

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Abstract

25 Citations

42 Claims

Specification

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Solutions

Use Cases

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