ELECTRONIC SYSTEM AND METHOD FOR DISPLAY USING A DECODER AND ARBITER TO SELECTIVELY ALLOW ACCESS TO A SHARED MEMORY
First Claim
Patent Images
1. An electronic system comprising:
- a bus couplable to a main memory having stored therein data corresponding to images to be decoded and also decoded data corresponding to images that have previously been decoded;
a decoder coupled to the bus for receiving compressed images and for outputting data for displaying the decoded images on a display device, the decoder receiving data from the main memory corresponding to at least one previously decoded image and to a current image to be decoded and outputting decoded data corresponding to a current image to be displayed, the current image being stored in the main memory;
a microprocessor system coupled to the main memory, the microprocessor system storing non-image data in and retrieving data from the main memory; and
an arbiter circuit coupled to both the microprocessor system and the decoder for controlling the access to said main memory by the decoder and the microprocessor.
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Abstract
An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.
41 Citations
20 Claims
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1. An electronic system comprising:
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a bus couplable to a main memory having stored therein data corresponding to images to be decoded and also decoded data corresponding to images that have previously been decoded;
a decoder coupled to the bus for receiving compressed images and for outputting data for displaying the decoded images on a display device, the decoder receiving data from the main memory corresponding to at least one previously decoded image and to a current image to be decoded and outputting decoded data corresponding to a current image to be displayed, the current image being stored in the main memory;
a microprocessor system coupled to the main memory, the microprocessor system storing non-image data in and retrieving data from the main memory; and
an arbiter circuit coupled to both the microprocessor system and the decoder for controlling the access to said main memory by the decoder and the microprocessor. - View Dependent Claims (2, 3, 4)
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5. A method of outputting data corresponding to an image to be displayed, comprising:
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storing within a main memory data corresponding to images to be decoded and also data corresponding to images that have previously been decoded;
transferring from the memory to a decoder on a first bus, data corresponding to an image to be decoded;
transferring from the main memory to a decoder data corresponding to images that have been previously decoded;
decoding, within the decoder, the current image using data corresponding to the current image and also using data corresponding to one or more previously decoded images;
outputting to the main memory data corresponding to the current image most recently decoded;
storing in the main memory decoded data corresponding to the most recently decoded image;
processing data that does not contain image information within a microprocessor;
storing the non-image data in said main memory by transferring the data from the microprocessor on the first bus;
transferring the non-image data from the main memory to the microprocessor on the first bus;
receiving signals in an arbitration circuit from the decoder and from the microprocessor; and
arbitrating access to said main memory via the arbitration circuit between the decoder and microprocessor. - View Dependent Claims (19)
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6. An electronic system comprising:
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a fast bus couplable a main memory having stored therein data corresponding to images to be decoded, decoded data corresponding to images that have previously been decoded, and non-image data that contains information other than image information and does not contain any image information;
a plurality of bus interfaces coupled to the fast bus;
a decoder coupled to the main memory via a first bus interface and adapted to receive compressed images and output a data stream of decoded images adapted to be displayed on a display device, the decoder receiving data from the main memory corresponding to at least one previously decoded and to a current image to be decoded and outputting decoded data corresponding to a current image to be displayed, the current image being stored in the main memory;
a central processing circuit coupled to the main memory via a second bus interface, the central processing circuit storing non-image data in and retrieving non-image data from the main memory; and
an arbiter circuit coupled to the decoder and to the second bus interface of the central processing circuit for controlling access to the bus via the respective bus interfaces of data to and from the first bus interface of the central processing circuit and the decoder.
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7. An electronic circuit for use with a bus coupled to a system memory and a device, comprising:
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a video decoder coupled to the bus for receiving compressed video images and for outputting video data for displaying the video decoded images on a display device, the video decoder configured to receive data from the system memory corresponding to at least one previously decoded image and to a current image to be decoded and configured to output decoded data corresponding to a current image to be displayed, the current image being stored in system memory; and
a memory arbiter coupled to both the device and the video decoder configure to control access to the system memory by the video decoder and the device. - View Dependent Claims (8, 9, 10, 11, 12, 20)
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13. An electronic circuit for use with a memory, comprising:
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a bus couplable to the memory;
a decoder coupled to the bus for receiving compressed images and for outputting data for displaying the decoded images on a display device, the decoder receiving data from the memory corresponding to at least one previously decoded image and to a current image to be decoded and outputting decoded data corresponding to a current image to be displayed, the current image being stored in the memory;
a central processing unit coupled to the bus for accessing memory; and
an arbiter coupled to the decoder and to the central processing unit for controlling access to the bus. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification
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Current AssigneeParthenon Unified Memory Architecture LLC (Acacia Research Corporation)
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Original AssigneeSTMicroelectronics Incorporated (STMicroelectronics NV)
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InventorsOwen, Jefferson, Colavin, Osvaldo, Diaz, Raul
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current345/535
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CPC Class CodesG06F 13/1605 based on arbitration arbitr...G06F 13/18 based on priority control G...G06F 15/167 using a common memory, e.g....G06T 1/60 Memory managementG09G 2340/02 Handling of images in compr...G09G 2360/18 Use of a frame buffer in a ...G09G 5/001 Arbitration of resources in...G09G 5/363 Graphics controllersH04N 19/423 characterised by memory arr...H04N 19/427 Display on the fly, e.g. si...H04N 19/61 in combination with predict...H04N 21/443 OS processes, e.g. booting ...H04N 21/4435 Memory management allocatio...
