SCHEME FOR ERASURE LOCATOR POLYNOMIAL CALCULATION IN ERROR-AND-ERASURE DECODER
First Claim
Patent Images
1. A method to generate an erasure locator polynomial in an error-and-erasure decoder, comprising the steps of:
- (A) storing a plurality of current values in a plurality of registers at a current one of a plurality of moments;
(B) generating a plurality of first values by multiplying each one of said current values by a respective one of a plurality of constants;
(C) generating a plurality of second values by gating at least all but one of said first values with a current one of plurality of erasure values of an erasure position vector;
(D) generating a plurality of next values by combining each one of said second values with a corresponding one of said first values;
(E) loading said next values into said registers in place of said current values at a next one of said moments; and
(F) generating an output signal carrying said current values at a last of said moments such that said current values form a plurality of coefficients of said erasure locator polynomial.
6 Assignments
0 Petitions
Accused Products
Abstract
A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial.
24 Citations
20 Claims
-
1. A method to generate an erasure locator polynomial in an error-and-erasure decoder, comprising the steps of:
-
(A) storing a plurality of current values in a plurality of registers at a current one of a plurality of moments; (B) generating a plurality of first values by multiplying each one of said current values by a respective one of a plurality of constants; (C) generating a plurality of second values by gating at least all but one of said first values with a current one of plurality of erasure values of an erasure position vector; (D) generating a plurality of next values by combining each one of said second values with a corresponding one of said first values; (E) loading said next values into said registers in place of said current values at a next one of said moments; and (F) generating an output signal carrying said current values at a last of said moments such that said current values form a plurality of coefficients of said erasure locator polynomial. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A circuit comprising:
-
a plurality of registers (i) storing a plurality of current values at a current one of a plurality of moments and (ii) generating an output signal carrying said current values at a last of said moments such that said current values form a plurality of coefficients of an erasure locator polynomial in an error-and-erasure decoder; a plurality of multiplier modules generating a plurality of first values by multiplying each one of said current values by a respective one of a plurality of constants; a plurality of first modules generating a plurality of second values by gating at least all but one of said first values with a current one of plurality of erasure elements of an erasure position vector; and a plurality of summing modules (i) generating a plurality of next values by combining each one of said second values with a corresponding one of said first values and (ii) loading said next values into said registers in place of said current values at a next one of said moments. - View Dependent Claims (9, 10, 11, 12, 13, 14)
-
-
15. A system comprising:
-
a first circuit configured to (i) receive an input codeword and an erasure location vector and (ii) generate an erasure locator polynomial in response to all of (a) said erasure location vector, (b) said input codeword and (c) a plurality of constant Galois field multipliers; a second circuit configured to generate a plurality of syndromes in response to said received codeword; and a third circuit configured to generate an output signal carrying a reconstructed codeword in response to all of (i) said erasure locator polynomial, (ii) said syndromes and (iii) said input codeword. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeAvago Technologies General IP PTE Limited (Broadcom, Inc.)
-
Original AssigneeLSI Corporation (Broadcom, Inc.)
-
InventorsAndreev, Alexander, Gasanov, Elyar E., Neznanov, Ilya V., Aliseychik, Pavel A., Panteleev, Pavel A.
-
Granted Patent
-
Time in Patent OfficeDays
-
Field of Search
-
US Class Current714/784
-
CPC Class CodesH03M 13/1515 Reed-Solomon codesH03M 13/153 using the Berlekamp-Massey ...H03M 13/1535 using the Euclid algorithmH03M 13/154 Error and erasure correctio...H03M 13/1545 Determination of error loca...H03M 13/159 Remainder calculation, e.g....
