GENERATION OF AN END POINT REPORT FOR A TIMING SIMULATION OF AN INTEGRATED CIRCUIT

US 20120246606A1
Filed: 12/08/2011
Published: 09/27/2012
Est. Priority Date: 03/21/2011
Status: Active Grant

First Claim

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1. A computer-readable storage medium storing machine executable instructions for a processor, wherein execution of the instructions cause the processor to:

load unit timing data from a timing simulation of an integrated circuit into a memory, wherein the unit timing data is descriptive of the timing at the upper hierarchy unit level;

load a selection of a unit timing path through the integrated circuit from the memoryload macro timing data from the timing simulation into the memory, wherein the integrated circuit comprises macros, wherein the macro timing data is descriptive of timing within the lower hierarchy macros during the simulation;

replace at least a portion of a unit timing end point report with the macro timing data along the unit timing path, wherein the unit timing report comprises the unit timing data, wherein the macro timing data replaces at least a portion of the unit timing data;

compute arrival times, slacks, and slews for the unit timing path using the replaced unit timing data;

compute path statistics in accordance with the arrival times, slacks and slews; and

generate an end point report for the unit timing path including the path statistics.

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Abstract

A computer-readable storage storing instructions for a processor. Execution of the instructions causes loading unit timing data descriptive of an upper hierarchy. Execution of the instructions cause the loading of a unit timing path, and the loading of macro timing data into the memory. Execution of the instructions further cause the replacement of at least a portion of the unit timing report with the macro timing data, and computation of arrival times, slacks, and slews. Execution of the instructions also cause computation of path statistics in accordance with the arrival times, slacks and slews, and generation of a end point report for the unit timing path, including path statistics.

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20 Claims

1. A computer-readable storage medium storing machine executable instructions for a processor, wherein execution of the instructions cause the processor to:
- load unit timing data from a timing simulation of an integrated circuit into a memory, wherein the unit timing data is descriptive of the timing at the upper hierarchy unit level;
  
  load a selection of a unit timing path through the integrated circuit from the memoryload macro timing data from the timing simulation into the memory, wherein the integrated circuit comprises macros, wherein the macro timing data is descriptive of timing within the lower hierarchy macros during the simulation;
  
  replace at least a portion of a unit timing end point report with the macro timing data along the unit timing path, wherein the unit timing report comprises the unit timing data, wherein the macro timing data replaces at least a portion of the unit timing data;
  
  compute arrival times, slacks, and slews for the unit timing path using the replaced unit timing data;
  
  compute path statistics in accordance with the arrival times, slacks and slews; and
  
  generate an end point report for the unit timing path including the path statistics.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
- - 2. The computer readable storage medium of claim 1, wherein execution of the instructions further causes the processor to recalculate the arrival times and the slacks of the replaced unit timing data in accordance with the unit timing end point report.
  - 3. The computer readable storage medium of claim 2, wherein the generating the end point report comprises summarizing assertion data from the macro and unit timing data adjacent to the arrival times and/or the slacks.
  - 4. The computer readable storage medium of claim 1, wherein execution of the instructions cause the processor to identify the unit timing path in accordance with the unit timing data.
  - 5. The computer readable storage medium of claim 1, wherein a selection of a plurality of unit timing paths is received, wherein the end point report is generated for each of the plurality of unit timing paths.
  - 6. The computer readable storage medium of claim 1, wherein a selection of all unit timing paths is received, wherein the end point report is generated for all of the unit timing paths.
  - 7. The computer readable storage medium of claim 1, wherein the path statistics comprise any one of the following:
    - total path delay, total wire delay, relative wire delay, the total buffer delay, the relative buffer delay, the total wiring delay, the relative wiring delay, total macro delay calculated at the macro level, total macro delay calculated for each macro, relative macro delay, total macro wire delay, relative macro wire delay, and combinations thereof.
  - 8. The computer readable storage medium of claim 1, wherein the unit timing data comprises any one of the following:
    - a higher hierarchy end point report filtered by slack threshold, clock phase, and component name, a higher hierarchy comprehensive report filtered by clock phase and component name, wirecode data, assertions, unit assertions, manually maintained assertion, contract files used to optimally generate new assertions from unit timing, and combinations thereof.
  - 9. The computer readable storage medium of claim 1, wherein the macro timing data comprises any one of the following:
    - macro end point report filtered by slack threshold and/or clock phase, macro comprehensive report, macro assertions, and combinations thereof.
  - 10. The computer readable storage medium of claim 1, wherein execution of the instructions further causes the processor to generate the unit timing data and the macro timing data by simulating the integrated circuit.
  - 11. The computer readable storage medium of claim 10, wherein the unit timing end point report and the macro timing data are calculated iteratively.
  - 12. The computer readable storage medium of claim 1, wherein execution of the instructions further causes the processor to:
    - detect a set of slew violations over all hierarchy levels of the timing path in the end point report, wherein the set of slew violations are identified for both macro and unit timing points; and
      
      generate a slew violation report using the set of slew violations.

13. A computer system comprising a processor, wherein the computer system further comprises a computer readable storage medium storing machine executable instructions, wherein execution of the instructions cause the processor to:
- load unit timing data from a timing simulation of an integrated circuit into a memory, wherein the unit timing data is descriptive of the timing at the upper hierarchy unit level;
  
  load a selection of a unit timing path through the integrated circuit from the memoryload macro timing data from the timing simulation into the memory, wherein the integrated circuit comprises macros, wherein the macro timing data is descriptive of timing within the lower hierarchy macros during the simulation;
  
  replace at least a portion of a unit timing end point report with the macro timing data along the unit timing path, wherein the unit timing end point report comprises unit timing data, wherein the macro timing data replaces at least a portion of the unit timing data;
  
  compute arrival times, slacks, and slews for the unit timing path using the replaced unit timing data;
  
  compute path statistics in accordance with the arrival times, slacks and slews; and
  
  generate an end point report for the unit timing path including the path statistics.
- View Dependent Claims (14, 15, 16, 17, 18, 19)
- - 14. The computer system of claim 13, wherein execution of the instructions further causes the processor to recalculate the arrival times and the slacks of the replaced unit timing data in accordance with the unit timing end point report.
  - 15. The computer system of claim 14, wherein the generating the end point report comprises summarizing assertion data from the macro and unit timing data adjacent to the arrival times and/or the slacks.
  - 16. The computer system of claim 13, wherein execution of the instructions cause the processor to identify the unit timing path in accordance with the unit timing data.
  - 17. The computer system of claim 13, wherein a selection of a plurality of unit timing paths is received, wherein the end point report is generated for each of the plurality of unit timing paths.
  - 18. The computer system of claim 13, wherein a selection of all unit timing paths is received, wherein the end point report is generated for all of the unit timing paths.
  - 19. The computer system of claim 13, wherein execution of the instructions further causes the processor to:
    - detect a set of slew violations over all hierarchy levels of the timing path in the end point report, wherein the set of slew violations are identified for both macro and unit timing points; and
      
      generate a slew violation report using the set of slew violations.

20. A computer-implemented method comprising:
- loading unit timing data from a timing simulation of an integrated circuit into a memory, wherein the unit timing data is descriptive of the timing at the upper hierarchy unit level;
  
  loading a selection of a unit timing path through the integrated circuit from the memoryloading macro timing data from the timing simulation into the memory, wherein the integrated circuit comprises macros, wherein the macro timing data is descriptive of timing within the lower hierarchy macros during the simulation;
  
  replacing at least a portion of a unit timing end point report with the macro timing data along the unit timing path, wherein the unit timing end point report comprises unit timing data, wherein the macro timing data replaces at least a portion of the unit timing data;
  
  computing arrival times, slacks, and slews for the unit timing path using the replaced unit timing data;
  
  computing path statistics in accordance with the arrival times, slacks, and slews; and
  
  generating an end point report for the unit timing path including the path statistics.

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Current Assignee
GlobalFoundries, Inc.
Original Assignee
International Business Machines Corporation
Inventors
WOERNER, Alexander, KRAUCH, Ulrich, LIND, Kurt

Granted Patent

US 8,522,182 B2
Time in Patent Office

Days
Field of Search
US Class Current

716/113
CPC Class Codes

G06F 2119/12 Timing analysis or timing o...

G06F 30/3312 Timing analysis

GENERATION OF AN END POINT REPORT FOR A TIMING SIMULATION OF AN INTEGRATED CIRCUIT

First Claim

4 Assignments

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Abstract

6 Citations

20 Claims

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GENERATION OF AN END POINT REPORT FOR A TIMING SIMULATION OF AN INTEGRATED CIRCUIT

First Claim

4 Assignments

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0 Petitions

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Accused Products

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Abstract

6 Citations

20 Claims

Specification

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