Method for programming a floating gate memory device

DC CAFC

US 5,042,009 A
Filed: 12/09/1988
Issued: 08/20/1991
Est. Priority Date: 12/09/1988
Status: Expired due to Term

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1. A method for programming a floating gate transistor, said floating gate transistor comprising a source, a drain spaced apart from said source, said source and drain being of a first conductivity type and formed in a semiconductor region of a second conductivity type, a channel extending between said source and drain, a floating gate extending over at least a portion of said channel, and a control gate extending over at least a portion of said floating gate, said method comprising the steps of:

applying a programming voltage to said drain and control gate sufficient to cause hot electron injection programming of said transistor; and

ensuring that the programming drain current for said transistor is less than a predetermined value.

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Abstract

A method of programming a floating gate transistor permits the use of a charge pump to provide drain programming current. The programming drain current is typically held below about 1 μA. This programming drain current can be provided by a conventional charge pump. In the first embodiment, the drain current can be limited by connecting a resistor between the source and ground. In a second embodiment, the drain current is limited by limiting the transistor control gate voltage. In a third embodiment, a charge pump is coupled to the drain while the control gate is repetitively pulsed. Each time the control gate is pulsed, the transistor turns on, and although the drain is initially discharged through the transistor, some hot electrons are accelerated onto the floating gate, and eventually the floating gate is programmed. In these embodiments the erase gate voltage may be raised to enhance programming efficiency.

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30 Claims

1. A method for programming a floating gate transistor, said floating gate transistor comprising a source, a drain spaced apart from said source, said source and drain being of a first conductivity type and formed in a semiconductor region of a second conductivity type, a channel extending between said source and drain, a floating gate extending over at least a portion of said channel, and a control gate extending over at least a portion of said floating gate, said method comprising the steps of:
- applying a programming voltage to said drain and control gate sufficient to cause hot electron injection programming of said transistor; and
  
  ensuring that the programming drain current for said transistor is less than a predetermined value.
- View Dependent Claims (2, 3, 4, 7, 8, 27, 28)
- - 2. Method of claim 1 wherein said predetermined value is less than or equal to about 150 μ
    - A.
  - 3. Method of claim 1 wherein said predetermined value is less than or equal to about 10 μ
    - A.
  - 4. Method of claim 1 wherein said programming drain voltage is provided by a charge pump and said programming drain current is held to a value sufficiently low so that said charge pump can provide said programming drain current.
  - 7. Method of claim 1 wherein said step of ensuring comprises the step of applying a voltage to said control gate to keep the drain current below said predetermined value.
  - 8. Method of claim 7 wherein said transistor comprises an erase gate capacitively coupled to said floating gate, said method further comprising the step of raising the voltage at said erase gate.
  - 27. Method of claim 1 wherein said step of ensuring comprises the step of coupling the source of said floating gate transistor to an additional transistor, said additional transistor limiting the current of said floating gate transistor during programming.
  - 28. Method of claim 1 wherein said step of ensuring comprises the step of raising the source voltage of said floating gate transistor during programming.

5. A method for programming a floating gate transistor, said floating gate transistor comprising a source, a drain spaced apart from said source, said source and drain being of a first conductivity type and formed in a semiconductor region of a second conductivity type, a channel extending between said source and drain, a floating gate extending over at least a portion of said channel, and a control gate extending over at least a portion of said floating gate, said method comprising the steps of:
- applying a programming voltage to said drain; and
  
  applying to said control gate a voltage which rises from a first value to a second value such that during the time said voltage at said control gate is rising, electrons are being injected into said floating gate so that the threshold voltage of said transistor increases at a rate which ensures that said transistor does not draw a drain current over a predetermined value during programming.
- View Dependent Claims (6)
- - 6. Method of claim 5 wherein the voltage applied to said control gate rises from said first value to said second value over a 0.1 ms time period.

9. A method for programming a floating gate transistor, said floating gate transistor comprising a source, a drain spaced apart from said source, said source and drain being of a first conductivity type and formed in a semiconductor region of a second conductivity type, a channel extending between said source and drain, a floating gate extending over at least a portion of said channel, and a control gate extending over at least a portion of said floating gate, said method comprising the steps of:
- applying a programming voltage to said drain and control gate;
  
  ensuring that the programming drain current is less than a predetermined value, wherein said step of ensuring comprises the step of providing an electrical resistance between said source and ground, said semiconductor region being grounded.
- View Dependent Claims (10, 11, 12, 13)
- - 10. Method of claim 9 wherein said transistor comprises an erase gate capacitively coupled to said floating gate, said method further comprising the step of raising the voltage at said erase gate.
  - 11. Method of claim 10 wherein the voltage at said erase gate is greater than 5 volts during programming.
  - 12. Method of claim 10 wherein the voltage at said erase gate is less than 20 volts during programming.
  - 13. Method of claim 9 wherein said transistor comprises an erase gate which is grounded during programming.

14. A method for programming a floating gate transistor, said transistor comprising a source, a drain, a channel extending between said source and drain, a floating gate extending over at least a portion of said channel, and a control gate extending over at least a portion of said floating gate, said method comprising the steps of:
- coupling a programming voltage generator to said drain; and
  
  repetitively applying pulses to said control gate to thereby cause hot electron injection programming of said transistor.
- View Dependent Claims (15, 16, 17)
- - 15. Method of claim 14 wherein said programming voltage generator is a charge pump.
  - 16. Method of claim 14 wherein said transistor comprises an erase gate capacitively coupled to said floating gate, said method further comprising the step of raising the voltage at said erase gate.
  - 17. Method of claim 14 wherein said transistor comprises an erase gate which is grounded during programming.

18. A method for programming a floating gate transistor, said transistor comprising a source, a drain, a channel extending between said source and drain, a floating gate extending over at least a portion of said channel, and a control gate extending over at least a portion of said floating gate, said method comprising the steps of:
- coupling a programming voltage generator to said drain; and
  
  repetitively applying pulses to said control gate,wherein said programming voltage generator is incapable of generating an output current which said transistor would normally conduct if (1) said floating gate were unprogrammed, (2) said programming drain voltage was applied to said drain, and (3) a programming control gate voltage equal to the amplitude of said pulses was applied to said control gate.

19. Structure comprising:
- a floating transistor including a source, a drain spaced apart from said source, said source and drain being of a first conductivity type and formed in a semiconductor region of a second conductivity type, a channel extending between said source and drain, a floating gate extending over at least a portion of said channel, and a control gate extending over at least a portion of said floating gate; and
  
  means for applying a programming voltage to said drain and control gate to thereby program said transistor by hot electron injection and ensuring that the programming drain current of said transistor is less than a predetermined value.
- View Dependent Claims (20, 23, 24, 29, 30)
- - 20. Structure of claim 19 wherein said predetermined value is less than or equal to about 150 μ
    - A.
  - 23. Structure of claim 19 wherein an electrical resistance is provided between said source and ground to prevent said programming drain current from exceeding said predetermined value, said semiconductor region being grounded.
  - 24. Structure of claim 23 wherein said transistor comprises an erase gate capacitively coupled to said floating gate, and said means for applying also raises the voltage at said erase gate during programming.
  - 29. Structure of claim 19 further comprising means for increasing the voltage at said source during programming.
  - 30. Structure of claim 19 further comprising an additional transistor coupled to the source of said floating gate transistor, said additional transistor limiting the programming current of said floating gate transistor.

21. Structure comprising:
- a floating gate transistor including a source, a drain spaced apart from said source, said source and drain being of a first conductivity type and formed in a semiconductor region of a second conductivity type, a channel extending between said source and drain, a floating gate extending over at least a portion of said channel, and control gate extending over at least a portion of said floating gate; and
  
  means for applying a programming voltage to said drain and control gate and ensuring that the programming drain current is less than a predetermined value, wherein said means for applying applies to said control gate a voltage which rises from a first value to a second value such that during the time said voltage at said control gate is rising, electrons are being injected into said floating gate so that the threshold voltage of said transistor increases at a rate which ensures that said transistor does not draw a drain current over said predetermined value during programming.
- View Dependent Claims (22)
- - 22. Structure of claim 21 wherein said means for applying causes the voltage at said control gate to rise from said first value to said second value over a 0.1 ms time period.

25. Structure comprising:
- a floating gate transistor including a source, a drain, a channel extending between said source and drain, a floating gate extending over at least a portion of said channel, and a control gate extending over at least a portion of said floating gate; and
  
  means for repetitively applying pulses to said control gate to thereby program said floating gate transistor by hot electron injection.
- View Dependent Claims (26)
- - 26. Structure of claim 25 wherein said transistor includes an erase gate capacitively coupled to said floating gate, said structure further comprising means for raising the voltage at said erase gate during programming.

Specification

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Litigation Data

Current Assignee
United Module Corporation
Original Assignee
Waferscale Integration, Inc. (STMicroelectronics NV)
Inventors
Eitan, Boaz, Kazerounian, Reza
Primary Examiner(s)
Fears, Terrell W.

Application Number

US07/282,788
Time in Patent Office

984 Days
Field of Search

365/185, 365/189.01, 365/230.01
US Class Current

365/185.18
CPC Class Codes

G11C 16/0425   comprising cells containing...

G11C 16/10   Programming or data input c...

G11C 16/30   Power supply circuits

Method for programming a floating gate memory device

First Claim

2 Assignments

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Abstract

118 Citations

30 Claims

Specification

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Method for programming a floating gate memory device

First Claim

2 Assignments

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Litigations

0 Petitions

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Accused Products

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Abstract

118 Citations

30 Claims

Specification

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Solutions

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