Memories with burst mode access
DC
First Claim
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1. A memory comprising:
- a plurality of rows of memory locations;
a plurality of first registers, each first register for receiving a row address;
a plurality of row decoders, each row decoder for activating a portion of a row identified by signals from one of said first registers;
one or more sense amplifiers for amplifying contents of said memory locations in the row portions; and
an output for providing output signals from said sense amplifiers,wherein at least two locations L1 and L2 in different rows having different row addresses in said memory can be read out to said output in burst mode such that the memory receives an address of one of said locations and provides in response contents of a plurality of memory locations, including the locations L1 and L2, in the sequence of consecutive addresses, so that while one of said row decoders is activating a row portion comprising said location L1 and contents of said location L1 are being transferred from one or more of said sense amplifiers to said output, another one of said row decoders is activating a row portion comprising said location L2 and contents of said location L2 are being transferred from said location L2 to one or more of said sense amplifiers.
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Abstract
To provide a boundaryless burst mode access, a memory array is divided into two or more subarrays. Each subarray has its own row and column decoders. The columns of each subarray are divided into groups. A sense amplifier circuit is provided for each group of columns. The column decoder of each subarray selects simultaneously one column from each group so that the memory locations in one row in the selected columns have consecutive addresses. The memory locations in the selected row and columns are read by the sense amplifier circuits. While the contents of the sense amplifier circuits of one subarray are transferred one by one to the memory output, consecutive memory locations of another subarray are read to the sense amplifier circuits. In some embodiments, to save power, sense amplifier circuits are disabled when their outputs are not transferred to the memory output.
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Citations
23 Claims
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1. A memory comprising:
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a plurality of rows of memory locations; a plurality of first registers, each first register for receiving a row address; a plurality of row decoders, each row decoder for activating a portion of a row identified by signals from one of said first registers; one or more sense amplifiers for amplifying contents of said memory locations in the row portions; and an output for providing output signals from said sense amplifiers, wherein at least two locations L1 and L2 in different rows having different row addresses in said memory can be read out to said output in burst mode such that the memory receives an address of one of said locations and provides in response contents of a plurality of memory locations, including the locations L1 and L2, in the sequence of consecutive addresses, so that while one of said row decoders is activating a row portion comprising said location L1 and contents of said location L1 are being transferred from one or more of said sense amplifiers to said output, another one of said row decoders is activating a row portion comprising said location L2 and contents of said location L2 are being transferred from said location L2 to one or more of said sense amplifiers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 10, 13)
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8. A memory comprising:
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a set of consecutively addressed memory locations L1, . . . Ln; a plurality of sense amplifier circuits for amplifying contents of said memory locations; and an output for providing output signals from said plurality of sense amplifier circuits, wherein said memory has a burst mode operation for receiving an address and reading out to said output, in response to said address, any given number of memory locations in the sequence of consecutive addresses with wrap around so that the next location, if any, to be read out after said location Ln is said location L1, such that during said operation while the contents of any location L to be read out other than the last location to be read out are being transferred from said plurality of sense amplifier circuits to said output, the contents of another location to be read out after said location L are being provided to said plurality of sense amplifier circuits for amplification and subsequent transfer to said output, and wherein said memory further comprises a control circuit for selectively enabling said sense amplifier circuits so that said control circuit enables a sense amplifier circuit whose output signals are being transferred to the output of said memory but said control circuit does not enable all said sense amplifier circuits at the same time. - View Dependent Claims (9, 11, 12, 14)
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15. In a memory having a plurality of rows of memory locations and having a plurality of row decoders and one X-register for each said row decoder, a method of reading in a burst mode operation a plurality of consecutively addressed memory locations spanning more than one row, said method comprising the steps of:
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providing to said X-registers a row address of a first location to be read in said burst mode operation; for each row containing a location to be read in said burst mode operation, performing the steps of; providing by at least one of the X-registers to at least one of the row decoders signals identifying said row; activating by one of said row decoders at least a portion of said row; sensing and amplifying contents of at least one location of said row; and transferring amplified contents of at least one location of said row to an output of said memory; wherein for at least two locations L1 and L2 of said plurality which are in different rows having different row addresses in said memory, the step of sensing and amplifying the contents of said location L2 overlaps in time with the step of transferring the amplified contents of said location L1 to said output of said memory. - View Dependent Claims (16, 17, 18)
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19. In a memory comprising a set of consecutively addressed memory locations L1, . . . , Ln, and a plurality of sense amplifier circuits, a method of reading out in burst mode a sequence of locations addressed consecutively with wrap around so that the next location to be read out after location Ln is location L1, said method comprising the steps of:
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receiving an address of a first location to be read out in burst mode; and in response to said address, for each location of said sequence performing the steps; sensing and amplifying contents of said location; and transferring amplified contents of said location to an output of said memory, wherein for any location L of said sequence other than the last location to be read out in said sequence, the transferring step for the location L overlaps in time with the sensing and amplifying step for another location to be read out after said location L in said sequence; and
for at least one location LL of said sequence, before the sensing and amplifying step for said location LL, the sense amplifier circuit which is to perform the sensing and amplifying step for the location LL is enabled, and after the transferring step for location LL, the sense amplifier circuit that has performed the sensing and amplifying step for location LL is disabled, and another sense amplifier circuit which is to perform the sensing and amplifying step for another location to be read out in said sequence is enabled.
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20. An integrated memory comprising:
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an array of memory locations, the array comprising a plurality of subarrays, each subarray comprising a predetermined number of groups of columns of the memory locations such that for any given column position in a group, the memory locations in any given row in the columns at said given position in the groups of the subarray have consecutive addresses; one X-decoder for each subarray; one X-register for each X-decoder; one Y-decoder for each subarray; one Y-register for each Y-decoder; one Y-select circuit for each subarray, the Y-select circuit being responsive to the Y-decoder of the subarray to select all the columns that occupy a selected position in the groups of the subarray; a plurality of sense amplifier circuits for each subarray, each sense amplifier circuit for amplifying signals from a column selected by the Y-select circuit of the subarray; a memory output; and a control circuit for selecting one of the sense amplifier circuits to provide data to the memory output, wherein in a burst mode read operation, at least one X-register provides to its respective X-decoder signals identifying a row in one of the subarrays, and at least one Y-register provides to its respective Y-decoder signals identifying a position of columns in the groups of one of the subarrays. - View Dependent Claims (21, 22, 23)
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Specification
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Litigation Data
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Current AssigneeAdvanced Micro Devices, Inc.
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Original AssigneeAdvanced Micro Devices, Inc.
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InventorsCheng, Pearl P., Briner, Michael S., Yu, James C.
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Primary Examiner(s)RUDOLPH, REBECCA
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Application NumberUS08/328,337Time in Patent Office701 DaysField of Search395/425, 395/500, 395/484, 395/405, 395/421.07, 395/401, 395/481, 365/230, 365/230.04, 365/230.08, 365/238.5US Class Current711/157CPC Class CodesG06F 12/04 Addressing variable-length ...G11C 7/1018 Serial bit line access mode...Y02D 10/00 Energy efficient computing,...
