Computer having a single bus supporting multiple bus architectures operating with different bus parameters

DC CAFC

US 5,630,163 A
Filed: 05/26/1995
Issued: 05/13/1997
Est. Priority Date: 08/09/1991
Status: Expired due to Term

- Alert
- Pin

Associated Cases

Associated Defendants

First Claim

Patent Images

1. A data processing system comprising,a processor,a plurality of external bus devices connected to the processor for communicating with the processor at different times, said bus devices operating with different timing parameters that include different information transfer rates associated with different bus bandwidths,a plurality of special-purpose buses each connected to the processor and to one of the external devices and each operating at a different bus bandwidth corresponding to the bus bandwidth associated with the bus device to which it is connected,a single common bus connecting the plurality of external bus devices to the plurality of special-purpose buses, andbus processing means for controlling the bus bandwidth of the common bus, to correspond to the bus bandwidth associated with the external bus device that is communicating with the processor at any one of said different times.

View all claims

9 Assignments

Timeline View

Assignment View

Litigations

0 Petitions

Accused Products

Abstract

A data processing system including a central processing unit and control circuitry on a single chip connected by a common bus to two or more bus devices having different sets of bus parameters. A first set of bus parameters functions as a memory bus for transfers to and from main memory, a second set of bus parameters functions as an I/O bus for I/O device transfers and a third set of bus parameters functions as a video bus for transfers to a video display. Each set of bus parameters has different timing selected to maximize transfers for the particular bus function (main memory, I/O, video or other) implemented by the bus parameters.

59 Citations

View as Search Results

27 Claims

1. A data processing system comprising,a processor,a plurality of external bus devices connected to the processor for communicating with the processor at different times, said bus devices operating with different timing parameters that include different information transfer rates associated with different bus bandwidths,a plurality of special-purpose buses each connected to the processor and to one of the external devices and each operating at a different bus bandwidth corresponding to the bus bandwidth associated with the bus device to which it is connected,a single common bus connecting the plurality of external bus devices to the plurality of special-purpose buses, andbus processing means for controlling the bus bandwidth of the common bus, to correspond to the bus bandwidth associated with the external bus device that is communicating with the processor at any one of said different times.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
- - 2. The data processing system of claim 1 further including,a keyboard timed under control of a keyboard clock signal, keyboard control means having timing means for enabling and disabling said keyboard clock signal to conserve power consumption by said keyboard when said keyboard clock signal is disabled.
  - 3. The data processing system of claim 1 further including,a keyboard having actuated keys timed by a keyboard clock signal, said keyboard providing a keyboard busy signal in response to a key actuation,keyboard control means having timing means for enabling and disabling said keyboard clock signal in order to conserve power consumption by said keyboard when said keyboard clock signal is disabled, said timing means including a restart timer for periodically enabling said keyboard clock signal where said restart timer is reset by said keyboard busy signal.
  - 4. The data processing system of claim 1 wherein said special-purpose buses include internal address buses for providing internal addresses, wherein said common bus includes a common address bus for common addresses and wherein said system further includes memory mapping registers for mapping said internal addresses to said common addresses.
  - 5. The data processing system of claim 4 wherein said bus devices include PC card memory and wherein said mapping registers map said internal addresses to said PC card memory.
  - 6. The data processing system of claim 4 wherein said bus devices include main memory and PC card memory and wherein said mapping registers map said internal addresses to said PC card memory and to said main memory, said system further including means for storing a copy of PC card memory information in said main memory whereby said main memory operates as a cache for PC card memory.
  - 7. The data processing system of claim 1 wherein,said plurality of bus devices includes one or more memory devices and one or more input/output devices, andsaid plurality of special-purpose buses includes a memory bus and an I/O bus.
  - 8. The data processing system of claim 7 wherein one of said memory devices includes video memory and said memory bus includes a video bus.
  - 9. The data processing system of claim 7 wherein one of said memory devices is a main memory and said memory bus includes a main memory bus.
  - 10. The data processing system of claim 9 wherein said main memory includes DRAM memory and wherein said system includes an independent DRAM refresh timer and scheduler for performing refresh operations during processor cycles which do not access DRAM whereby greater utilization of the common bus is achieved.
  - 11. The data processing system of claim 7 wherein one of said memory devices is read-only and said memory bus includes a read-only memory bus connected by means of the common bus to the read-only memory.
  - 12. The data processing system of claim 7 wherein one of said memory devices is a non-volatile random access memory and said memory bus includes a non-volatile random access memory bus.

13. A data processing system comprising,a plurality of external bus devices connected to a processor for communicating with the processor at different times, said bus devices operating with different timing parameters that include different information transfer rates associated with different bus bandwidths, anda plurality of components for integration on a common semiconductor chip, includingthe processor,a plurality of special-purpose buses each connected to the processor and to one of the external devices and each operating at a different bus bandwidth corresponding to the bus bandwidth associated with the bus device to which it is connected,a single common bus connecting the plurality of external bus devices to the plurality of special-purpose buses, andbus processing means for controlling the bus bandwidth of the common bus, to correspond to the bus bandwidth associated with the external bus device that is communicating with the processor at any one of said different times.
- View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
- - 14. The data processing system of claim 13 wherein said special-purpose buses include internal address buses, internal data buses, and internal control buses for providing internal addresses, internal data, and internal control, wherein said common bus includes a common address bus, a common data bus, and a common control bus for receiving said internal addresses, said internal data, and said internal control, respectively.
  - 15. The data processing system of claim 13 wherein said special-purpose buses include internal address buses, internal data buses, and internal control buses for providing internal addresses, data, and control, wherein said common bus includes a common address bus, a common data bus, and a common control bus for common addresses, common data, and common control and wherein said connection means includes,a bus data unit for connecting said internal data bus to said common data bus,a bus control unit for connecting said internal control bus to said common control bus,a bus address unit for connecting said internal address bus to said common address bus.
  - 16. The data processing system of claim 13 further including,a keyboard timed under control of a keyboard clock signal, keyboard control means having timing means for enabling and disabling said keyboard clock signal to conserve power consumption by said keyboard when said keyboard clock signal is disabled.
  - 17. The data processing system of claim 13 further including,a keyboard having actuated keys timed by a keyboard clock signal, said keyboard providing a keyboard busy signal in response to a key actuation,keyboard control means having timing means for enabling and disabling said keyboard clock signal in order to conserve power consumption by said keyboard when said keyboard clock signal is disabled, said timing means including a restart timer for periodically enabling said keyboard clock signal where said restart timer is reset by said keyboard busy signal.
  - 18. The data processing system of claim 13 wherein said bus processing means includes,a processing unit state machine for determining a state of said bus processing means,a direct memory access state machine for determining a state of direct memory accesses,a wait state control for determining wait states in said data processing system.
  - 19. The data processing system of claim 13 wherein said special-purpose buses include internal address buses for providing internal addresses, wherein said common bus includes a common address bus for common addresses and wherein said system further includes memory mapping registers for mapping said internal addresses to said common addresses.
  - 20. The data processing system of claim 19 wherein said bus devices include PC card memory and wherein said mapping registers map internal addresses to said PC card memory.
  - 21. The data processing system of claim 19 wherein said bus devices include main memory and PC card memory and wherein said mapping registers map said internal addresses to said PC card memory and to said main memory, said data processing system further including means for storing a copy of PC card memory information in said main memory whereby said main memory operates as a cache for PC card memory.
  - 22. The data processing system of claim 13 wherein,said plurality of bus devices includes one or more memory devices and one or more input/output devices, andsaid plurality of special-purpose buses includes a memory bus and an I/O bus.
  - 23. The data processing system of claim 22 wherein one of said memory devices includes video memory and said memory bus includes a video bus.
  - 24. The data processing system of claim 22 wherein one of said memory devices is a main memory and said memory bus includes a main memory bus.
  - 25. The data processing system of claim 24 wherein said main memory includes DRAM memory and wherein said system includes an independent DRAM refresh timer and scheduler for performing refresh operations during processor cycles which do not access DRAM whereby greater utilization of the common bus is achieved.
  - 26. The data processing system of claim 22 wherein one of said memory devices is a read-only memory and said memory bus includes a read-only memory bus.

27. A data processing system for communicating with a plurality of external devices, said devices operating with different timing parameters that include different information transfer rates associated with different bus bandwidths, the data processing system comprisinga processor;
- a plurality of special-purpose buses each connected to the processor and to one of the external devices and each operating at a different bus bandwidth corresponding to the bus bandwidth associated with the bus device to which it is connected,a single common bus connecting the plurality of external bus devices to the plurality of special-purpose buses, andbus processing means for controlling the bus bandwidth of the common bus, to correspond to the bus bandwidth associated with the external bus device that is communicating with the processor at any one of said different times.

Specification

Resources

Litigation Campaign Assessment

Litigation Data

Current Assignee
St Clair Intellectual Property Consultants Incorporated
Original Assignee
Vadem Limited
Inventors
Mitchell, Phillip M., Tsang, Siu K., Farquhar, Norman P., Fung, Henry T.
Primary Examiner(s)
An, Meng-AI T.
Assistant Examiner(s)
Nguyen, Dzung C.

Application Number

US08/452,246
Time in Patent Office

718 Days
Field of Search

395/800, 395/200, 395/275, 395/200.13, 395/281, 395/282, 395/297, 395/306, 395/307, 395/865, 395/869, 364/DIG. 1, 364/238, 364/238.2, 364/238.3, 364/238.9
US Class Current

710/307
CPC Class Codes

G06F 13/4217   with synchronous protocol

G09G 2320/0247   Flicker reduction other tha...

G09G 3/2025   the sub-frames having all t...

G09G 3/3611   Control of matrices with ro...

G09G 5/222   Control of the character-co...

G09G 5/363   Graphics controllers

Y02D 10/00   Energy efficient computing,...

Computer having a single bus supporting multiple bus architectures operating with different bus parameters

First Claim

9 Assignments

Litigations

0 Petitions

Accused Products

Abstract

59 Citations

27 Claims

Specification

Solutions

Use Cases

Quick Links

Computer having a single bus supporting multiple bus architectures operating with different bus parameters

First Claim

9 Assignments

Subscription Required

Subscription Required

Litigations

0 Petitions

Subscription Required

Accused Products

Subscription Required

Abstract

59 Citations

27 Claims

Specification

Subscription Required

Solutions

Use Cases

Quick Links