Multi-mode power switching for computer systems

DC CAFC

US 5,758,175 A
Filed: 12/17/1996
Issued: 05/26/1998
Est. Priority Date: 06/01/1990
Status: Expired due to Term

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1. A computer system comprising a power management system and a plurality of computer system circuits including a CPU circuit, a plurality of input/output circuits, a memory circuit, and a system bus which directly connects the CPU circuit with the input/output circuits, said computer system adapted to perform a plurality of activities, wherein said power management system comprises:

an activity monitor which monitors the activity of the computer system including;

means for identifying each of said plurality of activities as either an active activity or an idle activity and for associating each of said plurality of activities with a predetermined activity value and with either a first arithmetic sign for activities identified as active activities or with a second arithmetic to said first sign for activities identified as idle activities;

an activity count accumulator for accumulating an activity count upon the occurrence of each of said plurality of activities including;

means for adding to a stored activity count, upon the occurrence of any one of said plurality of activities, a predetermined activity value associated with said particular activity; and

means for comparing the accumulated stored activity count with a conserve threshold and for causing a CONSERVE signal if the accumulated activity count has a predetermined algebraic relationship relative to the conserve threshold; and

a mode controller responsive to the activity monitor wherein the mode controller has a plurality of power modes of operation including a first mode and a second mode; and

a power control circuit coupled to said activity monitor which in response to the CONSERVE signal transitions from an ON state to a REDUCED state in which the power consumption of the computer is reduced relative to the power consumption in the ON state.

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Abstract

A power conservation system for use in a computer system. The power conservation system has an activity monitor and a plurality of modes of operation. The power conservation system has a power switching unit which couples the power supply to a selected group of the computer system circuits depending upon the power mode of operation. By controlling the power mode in response to the activity of the computer system, the power consumption of the computer system can be controlled.

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28 Claims

1. A computer system comprising a power management system and a plurality of computer system circuits including a CPU circuit, a plurality of input/output circuits, a memory circuit, and a system bus which directly connects the CPU circuit with the input/output circuits, said computer system adapted to perform a plurality of activities, wherein said power management system comprises:
- an activity monitor which monitors the activity of the computer system including;
  
  means for identifying each of said plurality of activities as either an active activity or an idle activity and for associating each of said plurality of activities with a predetermined activity value and with either a first arithmetic sign for activities identified as active activities or with a second arithmetic to said first sign for activities identified as idle activities;
  
  an activity count accumulator for accumulating an activity count upon the occurrence of each of said plurality of activities including;
  
  means for adding to a stored activity count, upon the occurrence of any one of said plurality of activities, a predetermined activity value associated with said particular activity; and
  
  means for comparing the accumulated stored activity count with a conserve threshold and for causing a CONSERVE signal if the accumulated activity count has a predetermined algebraic relationship relative to the conserve threshold; and
  
  a mode controller responsive to the activity monitor wherein the mode controller has a plurality of power modes of operation including a first mode and a second mode; and
  
  a power control circuit coupled to said activity monitor which in response to the CONSERVE signal transitions from an ON state to a REDUCED state in which the power consumption of the computer is reduced relative to the power consumption in the ON state.
- View Dependent Claims (2, 3, 4, 5, 6, 7)
- - 2. The computer system in claim 1, wherein said power control circuit further comprises:
    - a plurality of power switching circuits wherein each power switching circuit controls the power supply to one of the computer system circuits, and wherein each power switching circuit comprises;
      
      a switch which selectively couples a power supply to one of the computer system circuits;
      
      a plurality of memory cells associated with the switch including a first memory cell and a second memory cell;
      
      a multiplexer coupled to the switch and responsive to the mode controller;
      
      wherein the multiplexer couples the first memory cell to the switch in said first mode of the mode controller such that the state of the first memory cell controls whether the switch is open or closed; and
      
      wherein the multiplexer couples the second memory cell to the switch in said second mode of the mode controller such that the state of the second memory cell controls whether the switch is open or closed;
      
      whereby the power supply is selectively coupled to the plurality of computer system circuits and the power consumption of the computer system is controlled in response to the activity of the computer system.
  - 3. The computer system of claim 2 wherein the plurality of memory cells associated with the switch of each power switching circuit can be programmed by the CPU such that the status of the plurality of switches in each of the plurality of modes of operation of the mode controller is programmable.
  - 4. The computer system of claim 3 further comprising a polarity circuit coupled between each plurality of memory cells and each switch wherein the polarity circuit selectively inverts the output of the plurality of memory cells associated with each switch.
  - 5. The computer system of claim 2 wherein the mode controller has at least three modes of operation including a third mode;
    - wherein the switch of each power switching circuit is associated with a third memory cell; and
      
      wherein the multiplexer of each power switching circuit couples the third memory cell to the switch of each power switching circuit in said third mode of the mode controller such that the state of the third memory cell controls whether each switch is open or closed.
  - 6. The computer system of claim 5 wherein the plurality of memory cells associated with the switch of each power switching circuit can be programmed by the CPU such that the status of the plurality of switches in each of the plurality of modes of operation of the mode controller is programmable.
  - 7. The computer system of claim 5 further comprising a polarity circuit coupled between each plurality of memory cells and each switch wherein the polarity circuit selectively inverts the output of the plurality of memory cells associated with each switch.

8. A power management system for use in a computer system comprising a power supply, a plurality of computer system circuits including a CPU circuit, an input/output circuit, and a memory circuit, a system bus which connects the CPU circuit with said input/output circuit and said memory circuit, and a plurality of power control switches which selectively couple the power supply to at least some of the plurality of computer system circuits, said computer system performing a plurality of activities, wherein said power management system comprises:
- an activity monitor which monitors the activity of the computer system including monitoring said system bus which connects said CPU circuit with said input/output circuit and with said memory circuit and generates an activity indicator signal reflective of said monitored activity;
  
  said activity monitor including identification logic identifying each of said plurality of activities as either an active activity or an idle activity and for associating each of said plurality of activities with a predetermined activity value for each particular activity having magnitude and algebraic sign, an activity count accumulator for accumulating an activity count based on said magnitude and sign upon the occurrence of one of said activities, and a comparator for comparing the accumulated activity count with a threshold count and for causing said activity indicator signal if the accumulated activity count has a predetermined algebraic relationship relative to the threshold count;
  
  a mode controller establishing the mode of operation of said computer and responsive to the activity indicator signal of said activity monitor and having a plurality of modes of operation; and
  
  a power switching circuit comprising;
  
  a plurality of power control lines each for controlling the open or closed state of one of the plurality of power control switches;
  
  a memory cell associated with said plurality of control lines; and
  
  power director means which in response to the mode of operation established by said mode controller selectively couples each of the plurality of power control lines to said memory cell such that a signal is generated on the power control line that is dependent upon the state of the memory cell;
  
  said plurality of switches being controlled by the power switching circuit so that the power consumption of the computer system is controlled in response to the monitored activity of the computer system.
- View Dependent Claims (9, 10, 11)
- - 9. The power management system of claim 8 wherein the memory cell associated with each of the plurality of power control lines of the power switching circuit can be programmed by the CPU such that the status of the plurality of power control switches in each of the plurality of modes of operation of the mode controller is programmable.
  - 10. The computer system of claim 9 further comprising a polarity circuit coupled between each memory cell and each power control line wherein the polarity circuit selectively inverts the output of the memory cell associated with each power control line.
  - 11. The power management system of claim 8 wherein the mode controller has at least three modes of operation;
    - wherein each of the plurality of power control lines is associated with a bit stored in said memory cell;
      
      wherein said bit in said memory cell is alterable depending upon said mode; and
      
      wherein the power director means alters said bit to change control data on that power control line in each of the three modes of operation.

12. A power management system for use in a computer system comprising a power supply, a plurality of computer system circuits including a CPU circuit, an input/output circuit, and a memory circuit, a system bus which directly connects the CPU circuit with said input/output circuit and said memory circuit, and a plurality of power control switches which couple the power supply to provide operating power including bias voltages to transistors within said computer system circuits to the plurality of computer system circuits, wherein said power management system comprises:
- an activity monitor which monitors the activity of the computer system and generates an activity indicator signal reflective of said monitored activity;
  
  a mode controller responsive to the activity indicator signal of said activity monitor and having a plurality of modes of operation;
  
  a power switching circuit comprising;
  
  a plurality of power control lines each for controlling one of the plurality of power control switches;
  
  a memory cell associated with each of the plurality of control lines; and
  
  power director means which in response to the mode of operation of the mode controller selectively couples each of the plurality of power control lines to said memory cell associated with that power control line such that a signal is generated on the power control line that is dependent upon the state of the memory cell to which it is coupled;
  
  whereby the plurality of switches are controlled by the power switching circuit and the power consumption of the computer system is controlled in response to the activity of the computer system; and
  
  whereinthe mode controller has at least three modes of operation;
  
  each of the plurality of power control lines is associated with a bit stored in said memory cell;
  
  said bit in said memory cell is alterable depending upon said mode; and
  
  the power director means alters said bit to change control data on that power control line in each of the three modes of operation;
  
  said power director means includes a multiplexer circuit, and the power switching circuit further comprises a polarity circuit coupled to the output of the multiplexer and to a plurality of the plurality of power control lines;
  
  the polarity circuit comprises a plurality of polarity bits;
  
  each polarity bit has two states;
  
  in a first state of each polarity bit the polarity circuit inverts the signal on a corresponding power control line relative to the state of a corresponding associated memory cell; and
  
  wherein in the second state of each polarity bit the polarity circuit does not invert the signal on a corresponding power control line relative to the state of a corresponding associated memory cell.

13. A method for operating a computer system comprising a plurality of computer system circuits including a CPU circuit, a plurality of input/output circuits, and a memory circuit, a system bus which directly connects the CPU circuit with said plurality of input/output circuits and said memory circuit, a plurality of power control switches which selectively couple a power supply to the computer system circuits and having a plurality of functional power modes, wherein the method comprises the steps of:
- programming a first power control bit associated with each power control switch;
  
  programming a second power control bit associated with each power control switch;
  
  monitoring the activity of the computer system including identifying at least some of said plurality of activities as either active class or idle class activities and associating said at least some activities with an activity value having a magnitude component and algebraic sign component wherein said idle class activities have a sign opposite to said active class activities, accumulating an activity count as the sum of said activity values for each activity occurring during a predetermined monitoring period, and comparing the accumulated activity count with a threshold count and generating an indicator signal if the accumulated activity count has a predetermined algebraic relationship relative to the threshold count;
  
  switching the power mode of the computer system from a first mode to a second mode in response to said generated indicator signal indicating a first level of inactivity in the computer system;
  
  providing a signal to each of the plurality of power control switches dependent upon the state of the associated first power control bit in said first mode of the mode controller such that the state of that bit controls whether the switch is open or closed in said first mode; and
  
  providing a signal to each of the plurality of power control switches dependent upon the state of the associated second power control bit in said second mode of the mode controller such that the state of that bit controls whether the switch is open or closed in said second mode;
  
  whereby the power consumption of the computer system is controlled in response to the activity of the computer system.
- View Dependent Claims (14, 15)
- - 14. The method of claim 13 further comprising the step of:
    - programming a polarity control bit;
      
      and wherein the step of providing a signal to each of the plurality of power control switches dependent upon the state of the associated first power control bit in said first mode of the mode controller comprises the step of selectively inverting the signal provided to each of the plurality of power control switches relative to the state of the associated power control bit depending upon the state of the polarity control bit;
      
      and wherein the step of providing a signal to each of the plurality of power control switches dependent upon the state of the associated second power control bit in said second mode of the mode controller comprises the step of selectively inverting the signal provided to each of the plurality of power control switches relative to the state of the associated power control bit depending upon the state of the polarity control bit.
  - 15. The method of claim 13 further comprising the steps of:
    - programming a third power control bit associated with each of the plurality of power control switches;
      
      switching the power mode of the computer system from said second mode to a third mode in response to a second level of inactivity of the computer system;
      
      and providing a signal to each of the plurality of power control switches dependent upon the state of the associated third power control bit in said third mode of the computer system such that the state of that bit controls whether the switch is open or closed in third mode.

16. A method for operating a computer system comprising a plurality of computer system circuits including a CPU circuit, a plurality of input/output circuits, and a memory circuit, a system bus which directly connects the CPU circuit with said plurality of input/output circuits and said memory circuit, a plurality of power control switches which selectively couple a power supply to the computer system circuits and having a plurality of functional power modes, wherein the method comprises the steps of:
- programming a first power control bit associated with each power control switch;
  
  programming a second power control bit associated with each power control switch;
  
  monitoring the activity of the computer system and switching the power mode of the computer system from a first mode to a second mode in response to a first level of inactivity in the computer system;
  
  providing a signal to each of the plurality of power control switches dependent upon the state of the associated first power control bit in said first mode of the mode controller such that the state of that bit controls whether the switch is open or closed in said first mode;
  
  providing a signal to each of the plurality of power control switches dependent upon the state of the associated second power control bit in said second mode of the mode controller such that the state of that bit controls whether the switch is open or closed in said second mode;
  
  programming a third power control bit associated with each of the plurality of power control switches;
  
  switching the power mode of the computer system from said second mode to a third mode in response to a second level of inactivity of the computer system;
  
  providing a signal to each of the plurality of power control switches dependent upon the state of the associated third power control bit in said third mode of the computer system such that the state of that bit controls whether the switch is open or closed in third mode; and
  
  programming a polarity control bit;
  
  said step of providing a signal to each of the plurality of power control switches dependent upon the state of the associated first power control bit in said first mode of the mode controller further comprises the step of selectively inverting the signal provided to each of the plurality of power control switches relative to the state of the associated power control bit depending upon the state of the polarity control bit;
  
  said step of providing a signal to each of the plurality of power control switches dependent upon the state of the associated second power control bit in said second mode of the mode controller comprises the step of selectively inverting the signal provided to each of the plurality of power control switches relative to the state of the associated power control bit depending upon the state of the polarity control bit; and
  
  said step of providing a signal to each of the plurality of power control switches dependent upon the state of the associated second power control bit in said third mode of the mode controller comprises the step of selectively inverting the signal provided to each of the plurality of power control switches relative to the state of the associated power control bit depending upon the state of the polarity control bit;
  
  whereby the power consumption of the computer system is controlled in response to the activity of the computer system.

17. In a power consumption management system for a computer system having a plurality of computer system devices receiving operating power from a common computer power supply, said computer system devices including a CPU device, an input/output device, and a memory device, and a single common system bus which directly connects the CPU device with the input/output device and the memory device, and wherein said computer system is adapted to perform a plurality of activities and has an activity level and a power consumption level as a result of performance of at least one of said plurality of activities;
- an activity monitor comprising;
  
  means for identifying each of said plurality of activities as either an active activity or an idle activity and for associating each of said plurality of activities with a predetermined activity value and with either a first arithmetic sign for activities identified as active activities or with a second arithmetic sign opposite to said first sign for activities identified as idle activities;
  
  an activity count accumulator for accumulating an activity count during a first predetermined time interval upon the occurrence of each of said plurality of activities including means for adding to a stored activity count, upon the occurrence of any one of said plurality of activities, a predetermined activity value associated with said particular activity;
  
  a comparator for comparing the accumulated stored activity count within said first predetermined time interval with a first threshold and for generating a first conserve power signal if the accumulated activity count is equal to the first threshold; and
  
  means for withholding said operating power from any one or more selected ones of said plurality of computer system devices in response to said first conserve power signal.
- View Dependent Claims (18, 19)
- - 18. The activity monitor in claim 17, wherein said activity count accumulator further accumulates said activity count during a second predetermined time interval longer than said first interval;
    - wherein said comparator compares said count accumulated during said second interval with a second threshold and generates a second conserve power signal if the count accumulated during said second interval is equal to a second threshold; and
      
      wherein said means for withholding said operating power withholds operating power from any one or more selected ones of said plurality of computer system devices in response to said second conserve power signal, a number of devices from which said power is withheld being greater than the number of devices from which said operating power is withheld in response to said first conserve signal.
  - 19. The activity monitor in claim 18, wherein said activity count accumulator further accumulates said activity count during a third predetermined time interval longer than said second interval;
    - wherein said comparator compares said count accumulated during said third interval with a third threshold and generates a third conserve power signal if the count accumulated during said third interval is equal to a third threshold; and
      
      wherein said means for withholding said operating power withholds operating power from any one or more selected ones of said plurality of computer system devices in response to said third conserve power signal, a number of devices from which said power is withheld being greater than the number of devices from which said operating power is withheld in response to said second conserve signal.

20. In a power consumption management system for a computer system having a plurality of computer system devices receiving operating power from a common computer power supply, said computer system devices including a CPU device, an input/output device, and a memory device, and a system bus which connects the CPU device with the input/output device and the memory device, and wherein said computer system is adapted to perform a plurality of activities and has an activity level and a power consumption level as a result of performance of at least one of said plurality of activities;
- a method for monitoring activity of said computer system comprising the steps of;
  
  identifying each of said plurality of activities as either an active activity or an idle activity and associating each of said plurality of activities with a predetermined activity value and with either a first arithmetic sign for activities identified as active activities or with a second arithmetic sign opposite to said first sign for activities identified as idle activities;
  
  accumulating an activity count during a first predetermined time interval upon the occurrence of each of said plurality of activities including adding to a stored activity count, upon the occurrence of any one of said plurality of activities, a predetermined activity value associated with said particular activity;
  
  comparing the accumulated stored activity count within said first predetermined time interval with a first threshold and generating a first conserve power signal if the accumulated activity count is within a predetermined range of the first threshold; and
  
  withholding said operating power from any one or more selected ones of said plurality of computer system devices in response to said first conserve power signal.
- View Dependent Claims (21, 22)
- - 21. The activity monitor in claim 20, wherein step of accumulating an activity count further includes the step of accumulating said activity count during a second predetermined time interval longer than said first interval;
    - andsaid step of comparing further includes the step of comparing said count accumulated during said second interval with a second threshold and generating a second conserve power signal if the count accumulated during said second interval is within a predetermined range of a second threshold; and
      
      said step of withholding said operating power includes the step of withholding operating power from any one or more selected ones of said plurality of computer system devices in response to said generation of said second conserve power signal, a number of devices from which said power is withheld in response to generation of said second conserve signal being greater than the number of devices from which said operating power is withheld in response to said first conserve signal.
  - 22. The activity monitor in claim 21, wherein step of accumulating an activity count further includes the step of accumulating said activity count during a third predetermined time interval longer than said second interval;
    - said step of comparing further includes the step of comparing said count accumulated during said third interval with a third threshold and generating a third conserve power signal if the count accumulated during said third interval is within a predetermined range of a third threshold; and
      
      said step of withholding said operating power includes the step of withholding operating power from any one or more selected ones of said plurality of computer system devices in response to said generation of said third conserve power signal, a number of devices from which said power is withheld in response to generation of said third conserve signal being greater than the number of devices from which said operating power is withheld in response to said second conserve signal.

23. In a computer system having a power management system and a plurality of computer system circuits including a CPU circuit, a plurality of input/output circuits, a memory circuit, a power supply for providing electrical power to operate at least one of said computer system circuits, a clock circuit for generating a clock signal, and a system bus which connects the CPU circuit with the input/output circuits, and wherein said computer system is adapted to perform a plurality of activities, a method for managing power use by said computer system comprising the steps of:
- monitoring the activity of the computer system including the steps of;
  
  identifying each of said plurality of activities as either an active activity or an idle activity and associating each of said plurality of activities with a predetermined activity value and with either a first arithmetic sign for activities identified as active activities or with a second arithmetic sign opposite to said first sign for activities identified as idle activities;
  
  accumulating an activity count upon the occurrence of each of said plurality of activities including adding to a stored activity count, upon the occurrence of any one of said plurality of activities, a predetermined activity value associated with said particular activity; and
  
  comparing the accumulated stored activity count with a conserve threshold and for causing a conserve signal if the accumulated activity count has a predetermined algebraic relationship relative to the conserve threshold;
  
  controlling a power mode of operation in response to said conserve signal to select a mode of operation from among at least a first mode and a second mode; and
  
  controlling power consumption of said computer by transitioning operation of at least one of said computer system circuits from an on state to a reduced power state in response to the conserve signal in which the power consumption of the computer is reduced relative to the power consumption in the on state.
- View Dependent Claims (24, 25, 26, 27)
- - 24. The method in claim 23, wherein said step of controlling power consumption of said computer further comprises the step of controlling distribution of electrical power from said power supply to one of said computer system circuits.
  - 25. The method in claim 24, wherein said step of controlling distribution of electrical power further comprises the steps of:
    - associating at least some of said plurality of computer system circuits with a power control value for each of said on state and reduced state, wherein said on and reduced power control value identify whether power is to be provided to or withheld from said computer system circuits during operation in said on state and said reduced state; and
      
      switchably controlling the connection of said power supply to said at least some of said computer system circuits based on said on and reduced power control values.
  - 26. The method in claim 24, wherein said step of associating at least some of said plurality of computer system circuits with a power control value for each of said on state and said reduced state further comprises the steps of:
    - providing a plurality of control bits for each of said on and reduced power control values in said memory; and
      
      associating each said control bit with a group of said devices, wherein each said control bit can have a first logical state or a second logical state; and
      
      wherein said step of switchably controlling the connection of said power supply to said at least some of said computer system circuits based on said on and said reduced power control values further comprises the step controlling the connection of said power supply to said devices based on the logic state of said associated control bit to close a switch and thereby connect said power supply to said device when only when said control bit has said first logic state.
  - 27. The method in claim 23, wherein said step of controlling power consumption of said computer further comprises the step of controlling the frequency of said clock signal distributed to one of said computer system circuits.

28. A computer system comprising a power management system and a plurality of computer system circuits including a processor circuit, at least one input/output circuit, a memory circuit, and a bus which connects the processor circuit with the input/output circuit, said computer system adapted to perform a plurality of processing activities, wherein said power management system comprises:
- an activity monitor which monitors the processing activity of said computer system including;
  
  identification logic identifying each of said plurality of activities as either an active class activity or an idle class activity and associating each of said plurality of activities with a predetermined activity value and with either a first arithmetic sign for activities identified as active class activities or with a second arithmetic sign opposite to said first sign for activities identified as idle class activities;
  
  an activity count accumulator for accumulating an activity count upon the occurrence of each of said plurality of activities including and adder for adding to a previous activity count, upon the occurrence of any one of said plurality of activities, a predetermined activity value associated with said particular activity; and
  
  a comparator coupled to said accumulator to receive said accumulated activity count and for comparing the accumulated activity count with a conserve threshold and for causing a conserve signal if the accumulated activity count has a predetermined algebraic relationship relative to the conserve threshold;
  
  a mode controller responsive to the activity monitor wherein the mode controller has a plurality of power modes of operation including a first mode and a second mode; and
  
  a control circuit coupled to said activity monitor and responsive to said activity monitor which in response to the conserve signal transitions said computer system from an on state to a reduced power consumption state in which the power consumption of the computer system is reduced relative to the power consumption in the on state by either;
  
  (i) removing a clock signal communicated to at least one of said computer system circuits, (ii) reducing the operating frequency of a clock signal communicated to at least one of said computer system circuits, (iii) reducing the electrical power delivered to at least one of said computer system circuits, or (iv) by a combination thereof.

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Litigation Data

Current Assignee
Amhus, Inc.
Original Assignee
Vadem Limited
Inventors
Fung, Henry Tat-Sang
Primary Examiner(s)
Bowler, Alyssa H.
Assistant Examiner(s)
FOLLANSBEE, JOHN A

Application Number

US08/768,331
Time in Patent Office

525 Days
Field of Search

395/800, 395/750, 395/750.05, 395/750.03, 395/750.01
US Class Current

713/323
CPC Class Codes

B01J 2219/00315   Microtiter plates

B01J 2219/00317   Microwell devices, i.e. hav...

B01J 2219/00605   the compounds being directl...

B01J 2219/00659   Two-dimensional arrays

B01J 2219/00686   Automatic

B01J 2219/00691   using robots

B01J 2219/00707   separated from the reactor ...

C40B 60/14   for creating libraries

G06F 1/3203   Power management, i.e. even...

G06F 1/3209   Monitoring remote activity,...

G06F 1/3215   Monitoring of peripheral de...

G06F 1/3221   of disk drive devices

G06F 1/324   by lowering clock frequency

G06F 1/3287   by switching off individual...

Y02D 10/00   Energy efficient computing,...

Y02D 30/50   in wire-line communication ...

Multi-mode power switching for computer systems

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Multi-mode power switching for computer systems

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