System and method of computer operating mode control for power consumption reduction

DC CAFC

US 6,079,025 A
Filed: 07/23/1998
Issued: 06/20/2000
Est. Priority Date: 06/01/1990
Status: Expired due to Term

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1. In a computer system comprising as hardware a plurality of system resources including a central processing unit (CPU), a memory device, and an input/output device, and as software, an operating system for managing and controlling said system resources, said system being operable in any one of at least three operating modes including a first-mode having a first power consumption level, a second-mode having a second power consumption level less than said first power consumption level, and a third-mode having a third power consumption level less than said second power consumption level;

a method for controlling the operating mode of said computer system comprising;

while operating in said first mode, monitoring said computer to detect execution of a predefined code thread, and generating a first-mode to second-mode transition command signal in response to said detecting execution of a predefined code thread; and

changing said operating mode from said first-mode to said second-mode in response to said first-mode to second-mode transition command signal; and

while operating in said second mode, monitoring said computer to detect occurrence or non-occurrence of a second predefined event, and generating a second-mode to third-mode transition command signal in response to said second event detection; and

changing said operating mode from said second-mode to said third-mode in response to said second-mode to third-mode transition command signal;

said first operating mode characterized by maintaining clocking of said CPU at a first frequency;

said second operating mode characterized by clocking said CPU at a second frequency less than said first frequency or by not maintaining clocking of said CPU; and

said third operating mode characterized by maintaining operation only of said memory to preserve the integrity of data stored therein.

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Abstract

An activity sensing power reduction and conservation apparatus, system, and method for a computer system. The computer system has resources including a processor, a memory, and an input/output device, and an operating system for controlling the resources. At least one of the resources can be placed into in any one of three operating modes including a first mode having a first power consumption level, a second mode having a second power consumption level less than the first level, and a third mode having a third level less than the second level. The first mode may be characterized by maintaining clocking of the processor at a first clock frequency, the second mode by clocking the processor at a second clock frequency less than the first frequency or by not maintaining clocking of the processor, and the third mode by maintaining operation of the memory to preserve the integrity of any stored memory contents. During operation of the computer system in the first mode, activity is monitored to detect completion of idle threads executing on the system, and the processor clock is slowed or stopped to at least that one resource in response to the idle thread completion detection. During operation in the second mode where the processor clock is slowed or stopped, a slow or stop resource command is generated to slow or turn off clock signal to at least one of the resources in response to occurrence of a timeout condition indication received from a timer circuit.

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48 Claims

1. In a computer system comprising as hardware a plurality of system resources including a central processing unit (CPU), a memory device, and an input/output device, and as software, an operating system for managing and controlling said system resources, said system being operable in any one of at least three operating modes including a first-mode having a first power consumption level, a second-mode having a second power consumption level less than said first power consumption level, and a third-mode having a third power consumption level less than said second power consumption level;
- a method for controlling the operating mode of said computer system comprising;
  
  while operating in said first mode, monitoring said computer to detect execution of a predefined code thread, and generating a first-mode to second-mode transition command signal in response to said detecting execution of a predefined code thread; and
  
  changing said operating mode from said first-mode to said second-mode in response to said first-mode to second-mode transition command signal; and
  
  while operating in said second mode, monitoring said computer to detect occurrence or non-occurrence of a second predefined event, and generating a second-mode to third-mode transition command signal in response to said second event detection; and
  
  changing said operating mode from said second-mode to said third-mode in response to said second-mode to third-mode transition command signal;
  
  said first operating mode characterized by maintaining clocking of said CPU at a first frequency;
  
  said second operating mode characterized by clocking said CPU at a second frequency less than said first frequency or by not maintaining clocking of said CPU; and
  
  said third operating mode characterized by maintaining operation only of said memory to preserve the integrity of data stored therein.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
- - 2. The method in claim 1, wherein said predefined code thread comprises an idle thread.
  - 3. The method in claim 2, wherein said second predefined event comprises occurrence of a timer timeout condition a predetermined period of time after initiation of execution of said first idle thread.
  - 4. The method in claim 2, wherein said second predefined event comprises occurrence of a predetermined timer timeout condition.
  - 5. The method in claim 4, wherein said step of turning off at least one device comprises turning off clock to all devices except said memory.
  - 6. The method in claim 1, wherein said execution of a predefined code thread comprises execution of a predefined code segment.
  - 7. The method in claim 6, wherein said predefined code segment comprises an operating system call.
  - 8. The method in claim 7, wherein said operating system call is an interrupt.
  - 9. The method in claim 8, wherein said operating system is selected from the group consisting of a multi-tasking operating system, Microsoft Windows, Microsoft DOS, and combinations thereof.
  - 10. The method in claim 8, wherein said interrupt comprises an idle state interrupt.
  - 11. The method in claim 10, wherein said idle state interrupt is selected from the group consisting of DOS Idle Handler (Interrupt 28h), and DOS Idle Call (Interrupt 2Fh Function 1680).
  - 12. The method in claim 8, wherein said interrupt comprises an idle handler.
  - 13. The method in claim 12, wherein said idle handler enables background operations while the system waits for input.
  - 14. The method in claim 12, wherein said idle handler is a operating system idle handler.
  - 15. The method in claim 14, wherein said operating system idle handler comprises DOS Interrupt 28h.
  - 16. The method in claim 14, wherein said operating system idle handler comprises DOS Multiplex Interrupt (Interrupt 2Fh).
  - 17. The method in claim 14, wherein said operating system idle handler comprises DOS Idle Call (Interrupt 2Fh Function 1680).
  - 18. The method in claim 12, wherein said idle handler comprises execution of an idle thread, and wherein execution of said idle thread communicates to other processes in said computer that the computer system is idle.
  - 19. The method in claim 8, wherein said operating system call is an operating system multiplex interrupt and is used to monitor inter-process communications to identify idle class calls.
  - 20. The method in claim 8, wherein said operating system call is an operating system multiplex interrupt and is used to monitor inter-process communications to identify operating system start-up and shut-down.
  - 21. The method in claim 7, wherein said operating system call informs the system that the operating system is idle.
  - 22. The method in claim 7, wherein said CPU is executing a plurality of threads and wherein each of said threads is in an idle state.
  - 23. The method in claim 22, wherein said threads have an idle class priority such that they do not execute unless there are no threads having higher execution priority than said idle class priority.
  - 24. The method in claim 22, wherein a keystroke check loop has an idle priority and is an indication of system idle.
  - 25. The method in claim 22, wherein herein said thread is any thread that gives an indication that the system is at idle.
  - 26. The method in claim 25, wherein said CPU generated command is selected from the group consisting of a system halt command, a system suspend command, and a system hibernate command.
  - 27. The method in claim 25, wherein said CPU generated command is generated whenever an idle thread has been executing for more than a predetermined period of time.
  - 28. The method in claim 1, wherein said first-mode to second-mode transition command slows or stops clocking of the CPU;
    - and wherein said second-mode to third-mode transition command signal slows or stops clocking of other of said system devices and resources with the proviso that inputs required for maintenance of data stored in said memory are maintained.
  - 29. The method in claim 1, wherein said second predetermined event comprises the occurrence of a second timer timeout.
  - 30. The method in claim 1, further comprising the steps of:
    - while operating in said third mode, monitoring said computer to detect occurrence or non-occurrence of a third predefined event, and generating a third-mode to first-mode transition command signal in response to said third event detection; and
      
      changing said operating mode from said third-mode to said first-mode in response to said third-mode to first-mode transition command signal.
  - 31. The method in claim 30, wherein said third event is selected from the group consisting of occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, and any predetermined interrupt.
  - 32. The method in claim 30, wherein said second predefined event is an event selected from the set consisting of a timeout event, a CPU command event, and a statistical evaluation event;
    - and wherein said third event is selected from the group consisting of occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, and any predetermined interrupt.
  - 33. The method in claim 30, further comprising the steps of:
    - while operating in said second mode, monitoring said computer to detect occurrence or non-occurrence of a fourth predefined event, and generating a second-mode to first-mode transition command signal in response to said fourth event detection; and
      
      changing said operating mode from said second-mode to said first-mode in response to said second-mode to first-mode transition command signal.
  - 34. The method in claim 33, wherein said fourth event is selected from the group consisting of a direct memory access (DMA), occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, any CPU initiated activity, any predetermined interrupt, and the occurrence of a predetermined address on a system bus.
  - 35. The method in claim 30, wherein said second predefined event is an event selected from the set consisting of a timeout event, a CPU command event, and a statistical evaluation event;
    - and wherein said third event is selected from the group consisting of an occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, and any predetermined interrupt; and
      
      wherein said fourth event is selected from the group consisting of a direct memory access (DMA), occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, any CPU initiated activity, any predetermined interrupt, and the occurrence of a predetermined address on a system bus.
  - 36. The method in claim 1, wherein said second predefined event is an event selected from the set consisting of a timeout event, a CPU command event, and a statistical evaluation event.
  - 37. The method in claim 1, further comprising the step of directly commanding said system to any of said first-mode, second-mode, or third mode by a CPU command.

38. In a computer system comprising as hardware a plurality of system resources including a central processing unit (CPU), a memory device, and an input/output device, and as software, an operating system for managing and controlling said system resources, said system being operable in any one of at least three operating modes including a first-mode having a first power consumption level, a second-mode having a second power consumption level less than said first power consumption level, and a third-mode having a third power consumption level less than said second power consumption level;
- a method for controlling the operating mode of said computer system comprising;
  
  while operating in said first mode, monitoring said computer to detect exceeding a threshold value for a statistical evaluation of active and idle process, and generating a first-mode to second-mode transition command signal in response to said detecting exceeding a threshold value for a statistical evaluation of active and idle process; and
  
  changing said operating mode from said first-mode to said second-mode in response to said first-mode to second-mode transition command signal; and
  
  while operating in said second mode, monitoring said computer to detect occurrence or non-occurrence of a second predefined event, and generating a second-mode to third-mode transition command signal in response to said second event detection; and
  
  changing said operating mode from said second-mode to said third-mode in response to said second-mode to third-mode transition command signal;
  
  said first operating mode characterized by maintaining clocking of said CPU at a first frequency;
  
  said second operating mode characterized by clocking said CPU at a second frequency less than said first frequency or by not maintaining clocking of said CPU; and
  
  said third operating mode characterized by maintaining operation only of said memory to preserve the integrity of data stored therein.
- View Dependent Claims (39, 40, 41)
- - 39. The method as in claim 38, wherein said idle process makes at least one function call.
  - 40. The method as in claim 38, wherein said idle process is comprised of threads.
  - 41. The method in claim 38, wherein said statistical evaluation comprises statistical evaluation of active and idle function calls.

42. In a computer system comprising as hardware a plurality of system resources including a central processing unit (CPU), a memory device, and an input/output device, and as software, an operating system for managing and controlling the system resources, at least one of said system devices and resources being operable in any one of three operating modes including a first-mode having a first power consumption level, a second-mode having a second power consumption level less than said first power consumption level, and a third-mode having a third power consumption level less than said second power consumption level;
- a method for controlling the operating mode of the computer system comprising the steps of;
  
  while operating in said first mode, monitoring said computer to detect completion of execution of all idle threads executing on said system, and generating a slow or stop processor clock command in response to said idle thread completion detection;
  
  while operating in said second mode wherein said CPU clock is slowed or stopped, receiving an interrupt from a timer circuit indicating occurrence of a predetermined timer time-out condition, and generating a slow or stop device command to slow or turn off clock signal to at least one of said devices in response to occurrence of said timeout condition;
  
  said first operating mode characterized by maintaining clocking of said CPU at a first clock frequency;
  
  said second operating mode characterized by clocking said CPU at a second clock frequency less than said first frequency or by not maintaining clocking of said CPU; and
  
  said third operating mode characterized by maintaining operation of said memory to preserve the integrity of memory contents stored therein.
- View Dependent Claims (43, 44, 45, 46, 47)
- - 43. The method in claim 42, further comprising the steps of:
    - while operating in said third mode, monitoring said computer to detect occurrence or non-occurrence of a third predefined event, and generating a third-mode to first-mode transition command signal in response to said third event detection; and
      
      changing said operating mode from said third-mode to said first-mode in response to said third-mode to first-mode transition command signal.
  - 44. The method in claim 43, wherein said third event is selected from the group consisting of occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, and a predetermined hardware interrupt.
  - 45. The method in claim 43, further comprising the steps of:
    - while operating in said second mode, monitoring said computer to detect occurrence or non-occurrence of a fourth predefined event, and generating a second-mode to first-mode transition command signal in response to said fourth event detection; and
      
      changing said operating mode from said second-mode to said first-mode in response to said second-mode to first-mode transition command signal.
  - 46. The method in claim 45, wherein said fourth event is selected from the group consisting of a direct memory access (DMA), occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, any CPU initiated activity, any predetermined interrupt, and the occurrence of a predetermined address on a system bus.
  - 47. The method in claim 42, wherein said first predefined event is an event selected from the set consisting of a timeout event, a CPU command event, and a statistical evaluation event;
    - and wherein said second predefined event is an event selected from the set consisting of a timeout event, a CPU command event, and a statistical evaluation event; and
      
      wherein said third event is selected from the group consisting of an occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, and any predetermined interrupt; and
      
      wherein said fourth event is selected from the group consisting of a direct memory access (DMA), occurrence of a keyboard input, modem ring indicator, real time clock alarm, external pushbutton, any CPU initiated activity, any predetermined interrupt, and the occurrence of a predetermined address on a system bus.

48. A computer system including as hardware a plurality of system resources including a processing unit responsive to a processor clock signal, a memory device, and an input/output device, and an operating system for controlling operation of said computer system, at least one of said system devices and resources being operable in any one of at least three operating modes including a first-mode having a first power consumption level, a second-mode having a second power consumption level less than said first power consumption level, and a third-mode having a third power consumption level less than said second power consumption level;
- said computer system characterized in that said computer system further comprises;
  
  idle thread execution completion detection means for monitoring said computer system to detect completion of execution of all idle threads executing on said system while operating in said first mode;
  
  processor clock speed control means for slowing or stopping said processor clock signal in response to said idle thread execution completion detection;
  
  a timer circuit generating a timer-timeout signal indicating occurrence of a predetermined timer time-out condition;
  
  a device controller receiving said timer-timeout signal while operating in said second mode wherein said processor clock is slowed or stopped and generating a slow or stop device signal to slow or turn off clock signal to at least one of said devices in response to occurrence of said timer timeout condition;
  
  said first operating mode characterized by maintaining clocking of said processor at a first clock frequency;
  
  said second operating mode characterized by clocking said processor at a second clock frequency less than said first frequency or by not maintaining clocking of said processor; and
  
  said third operating mode characterized by maintaining operation of said memory to preserve the integrity of memory contents stored therein.

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Current Assignee
St Clair Intellectual Property Consultants Incorporated
Original Assignee
Vadem Limited
Inventors
Fung, Henry Tat-Sang
Primary Examiner(s)
Sheikh, Ayaz R.
Assistant Examiner(s)
Wiley, David A.

Application Number

US09/121,352
Time in Patent Office

698 Days
Field of Search

713/300-340
US Class Current

713/323
CPC Class Codes

B01J 2219/00315   Microtiter plates

B01J 2219/00317   Microwell devices, i.e. hav...

B01J 2219/00605   the compounds being directl...

B01J 2219/00659   Two-dimensional arrays

B01J 2219/00686   Automatic

B01J 2219/00691   using robots

B01J 2219/00707   separated from the reactor ...

C40B 60/14   for creating libraries

G06F 1/3203   Power management, i.e. even...

G06F 1/3209   Monitoring remote activity,...

G06F 1/3215   Monitoring of peripheral de...

G06F 1/3221   of disk drive devices

G06F 1/324   by lowering clock frequency

G06F 1/3287   by switching off individual...

Y02D 10/00   Energy efficient computing,...

Y02D 30/50   in wire-line communication ...

System and method of computer operating mode control for power consumption reduction

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System and method of computer operating mode control for power consumption reduction

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Abstract

242 Citations

48 Claims

Specification

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