Systems and methods which utilize parity sets
DC CAFC
First Claim
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1. A memory system, comprising:
- a plurality of memory boards, each of the memory boards having a respective plurality of memory segments that may store respective data values, the segments being grouped into parity sets such that each of the parity sets includes respective segments of number N, the number N being an integer, the N respective segments in each respective parity set including a respective parity segment and N-1 respective data segments, the N respective segments in each respective parity set being distributed among the memory boards such that none of the memory boards has more than one respective segment from each respective parity set, and a respective data value stored in a respective parity segment in at least one parity set may be calculated by a logical exclusive-or of respective data values stored in respective data segments in the at least one parity set, wherein;
each memory board includes a respective plurality of memory regions, each memory region includes a respective subset of the segments included in a respective memory board, and each of the segments included in a respective memory region may be assigned a respective base memory address different from other respective base memory addresses that may be assigned to other segments included in the respective memory region.
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Abstract
A memory system and method of using same are provided. One embodiment of the system includes a semiconductor memory that is configured to include a multiplicity of memory segments. The memory segments are grouped into groups. Each of the groups includes N respective memory segments, where N is an integer number. In each respective group of memory segments, the N respective memory segments include respective data segments and a respective parity segment. Also in each respective group of memory segments, the respective parity segment in the respective group stores a respective data value P that may be calculated by a logical exclusive-or of respective data values stored in the respective data segments in the respective group.
69 Citations
18 Claims
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1. A memory system, comprising:
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a plurality of memory boards, each of the memory boards having a respective plurality of memory segments that may store respective data values, the segments being grouped into parity sets such that each of the parity sets includes respective segments of number N, the number N being an integer, the N respective segments in each respective parity set including a respective parity segment and N-1 respective data segments, the N respective segments in each respective parity set being distributed among the memory boards such that none of the memory boards has more than one respective segment from each respective parity set, and a respective data value stored in a respective parity segment in at least one parity set may be calculated by a logical exclusive-or of respective data values stored in respective data segments in the at least one parity set, wherein;
each memory board includes a respective plurality of memory regions, each memory region includes a respective subset of the segments included in a respective memory board, and each of the segments included in a respective memory region may be assigned a respective base memory address different from other respective base memory addresses that may be assigned to other segments included in the respective memory region. - View Dependent Claims (2, 3, 4, 5)
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6. A memory system, comprising:
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a plurality of semiconductor memory segments, the segments being grouped into groups, each of the groups including N respective semiconductor memory segments, the number N being an integer, the N respective segments in each respective group comprising respective data segments and a respective parity segment; and
in each of the groups;
the respective parity segment stores a respective data value P that may be calculated by a logical exclusive-or of respective data values stored in the respective data segments, wherein; the segments reside in memory regions of a memory board, and each of the segments included in a respective memory region may be assigned a respective base memory address different from other respective base memory addresses that may be assigned to other segments included in the respective memory region. - View Dependent Claims (7, 8, 9)
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10. A method of using a memory system, the memory system including a plurality of memory boards, each of the memory boards having a respective plurality of memory segments that may store respective data values, the method comprising:
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grouping the segments into parity sets such that each of the parity sets includes respective segments of number N, the number N being an integer, the N respective segments in each respective parity set including a respective parity segment and N-1 respective data segments;
distributing the N respective segments in each respective parity set among the memory boards such that none of the memory boards has more than one respective segment from each respective parity set; and
storing in a respective parity segment in at least one parity set a respective data value that may be calculated by logically exclusive-or-ing together respective data values stored in respective data segments in the at least one parity set, wherein;
each memory board includes a respective plurality of memory regions;
each memory region includes a respective subset of the segments included in a respective memory board; and
each of the segments included in a respective memory region may be assigned a respective base memory address different from other respective base memory addresses that may be assigned to other segments included in the respective memory region. - View Dependent Claims (11, 12, 13, 14)
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15. A method of using a memory system, the system comprising a plurality of semiconductor memory segments, the method comprising:
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grouping the segments into groups, each of the groups including N respective semiconductor memory segments, the number N being an integer, the N respective segments in each respective group comprising respective data segments and a respective parity segment; and
storing, in the respective parity segment in each of the groups, a respective data value P that may be calculated by logically exclusive-or-ing together respective data values stored in the respective data segments, wherein;
the segments reside in memory regions of a memory board of the system, and each of the segments included in a respective memory region may be assigned a respective base memory address different from other respective base memory addresses that may be assigned to other segments included in the respective memory region. - View Dependent Claims (16, 17, 18)
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Specification
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Litigation Data
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Current AssigneeEMC Corporation (Dell Technologies Inc.)
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Original AssigneeEMC Corporation (Dell Technologies Inc.)
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InventorsMacLellan, Christopher S., Walton, John K., Bermingham, Michael
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Primary Examiner(s)DILDINE JR, R STEPHEN
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Application NumberUS09/927,042Publication NumberTime in Patent Office1,398 DaysField of SearchG11/C02.9/00, 714/54, 714/763, 714/766, 714/773, 714/800, 714/805US Class Current714/766CPC Class CodesG06F 11/108 Parity data distribution in...G06F 2211/1009 Cache, i.e. caches used in ...
