Crypto-engine for cryptographic processing of data
DC CAFC
First Claim
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1. A crypto-engine for cryptographic processing of data comprising an arithmetic unit operable as a co-processor for a host processor and an interface controller for managing communications between the arithmetic unit and host processor, the arithmetic unit including:
- a memory unit for storing and loading data, the memory unit includingan input switch for selecting input-interim data;
a plurality of Static Random Access Memory elements for receiving and storing the input/interim data from the input switch;
a plurality of output switches connected to the memory elements; and
an address controller for controlling flow of the data through the switches and memory elementsa multiplication unit, an addition unit and a sign inversion unit for performing arithmetic operations on said data, the multiplication unit, the addition unit and the sign inversion unit each having an output; and
an arithmetic controller for controlling the storing and loading of data by the memory unit and for enabling the multiplication, addition and sign inversion units;
wherein the outputs of the multiplication unit, the addition unit and the sign inversion unit are feedback to the arithmetic controller.
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Abstract
A crypto-engine for cryptographic processing has an arithmetic unit and an interface controller for managing communications between the arithmetic unit and a host processor. The arithmetic unit has a memory unit for storing and loading data and arithmetic units for performing arithmetic operations on the data. The memory and arithmetic units are controlled by an arithmetic controller.
9 Citations
11 Claims
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1. A crypto-engine for cryptographic processing of data comprising an arithmetic unit operable as a co-processor for a host processor and an interface controller for managing communications between the arithmetic unit and host processor, the arithmetic unit including:
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a memory unit for storing and loading data, the memory unit including an input switch for selecting input-interim data; a plurality of Static Random Access Memory elements for receiving and storing the input/interim data from the input switch; a plurality of output switches connected to the memory elements; and an address controller for controlling flow of the data through the switches and memory elements a multiplication unit, an addition unit and a sign inversion unit for performing arithmetic operations on said data, the multiplication unit, the addition unit and the sign inversion unit each having an output; and an arithmetic controller for controlling the storing and loading of data by the memory unit and for enabling the multiplication, addition and sign inversion units; wherein the outputs of the multiplication unit, the addition unit and the sign inversion unit are feedback to the arithmetic controller. - View Dependent Claims (2, 3, 8)
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4. A crypto-engine for cryptographic processing of data comprising an arithmetic unit operable as a co-processor for a host processor and an interface controller for managing communications between the arithmetic unit and host processor,
the arithmetic unit including: -
a memory unit for storing and loading data; a multiplication unit, an addition unit and a sign inversion unit for performing arithmetic operations on said data, the multiplication unit, addition unit and sign inversion unit each having an output; and an arithmetic controller for controlling the storing and loading of data by the memory unit and for enabling the multiplication, addition and sign inversion units, wherein the outputs of the multiplication unit, an addition unit and a sign inversion unit are feedback to the arithmetic controller; the interface controller including; a bus interface for connecting high frequency manipulated data inside the arithmetic unit with the lower frequency manipulated data in the host processor; a concatenater/splitter for merging or splitting data width, and a cryptographic controller generating status and interrupt signals for the host processor and generating an op-code signal for the arithmetic unit, the arithmetic unit selecting RSA or EGO modes of operation based on the op-code signal. - View Dependent Claims (5, 6, 7, 9, 10, 11)
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Specification
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Litigation Data
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Current AssigneeLonghorn Automotive Group LLC (Alpha Alpha Intellectual Partners LLC)
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Original AssigneeCityU Research Limited
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InventorsCheng, Lee Ming, Ngan, Ting On, Hau, Ka Wai
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Primary Examiner(s)Kim, Jung
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Application NumberUS10/641,869Publication NumberTime in Patent Office2,314 DaysField of SearchNoneUS Class Current713/191CPC Class CodesH04L 2209/12 Details relating to cryptog...H04L 2209/20 Manipulating the length of ...H04L 9/302 involving the integer facto...H04L 9/3066 involving algebraic varieti...
