Adaptive power control
DC CAFC
First Claim
Patent Images
1. A computer system comprising:
- a processing unit operable at different voltages;
a second component; and
a frequency generator configured to receive a first clock signal from a clock generator and to adjust a frequency of said first clock signal to furnish clock signals at different frequencies to said processing unit and said second component, wherein said different frequencies are individually adjustable;
wherein, in response to initiating a change in frequency for said processing unit, said processing unit is configured to start a counter and to shut down clocks to said processing unit and said second component; and
wherein further, in response to said counter reaching a specified value, said processing unit is configured to turn on said clocks.
9 Assignments
Litigations
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Accused Products
Abstract
A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.
271 Citations
27 Claims
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1. A computer system comprising:
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a processing unit operable at different voltages; a second component; and a frequency generator configured to receive a first clock signal from a clock generator and to adjust a frequency of said first clock signal to furnish clock signals at different frequencies to said processing unit and said second component, wherein said different frequencies are individually adjustable;
wherein, in response to initiating a change in frequency for said processing unit, said processing unit is configured to start a counter and to shut down clocks to said processing unit and said second component; and
wherein further, in response to said counter reaching a specified value, said processing unit is configured to turn on said clocks. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computer system comprising:
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a processing unit operable at different voltages; a second component; a clock generator configured to generate a first clock signal at a frequency, said processing unit configured to register a value corresponding to an amount of time allowed for phase-locked-loop (PLL) circuitry to lock in response to a change in frequency of said first clock signal; and a frequency generator coupled to said clock generator and comprising said PLL circuitry, said frequency generator configured to adjust said frequency of said first clock signal to concurrently furnish clock signals at different frequencies to said processing unit and said second component, wherein said different frequencies are individually adjustable;
wherein, in response to initiating said change in frequency, said processing unit is configured to start a counter and to shut down clocks to said processing unit and said second component; and
wherein further, in response to said counter reaching said value, said processing unit is configured to turn on said clocks. - View Dependent Claims (11, 12, 13, 14, 15, 25)
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16. A method comprising:
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adjusting a first clock signal at a first frequency to provide a second clock signal at a second frequency to a processing unit of a computer system and a third clock signal at a third frequency to a second component of said computer system; monitoring operating conditions of said processing unit; changing a level of voltage furnished to said processing unit according to said operating conditions in response to initiation of a change in frequency for said processing unit, starting a counter and stopping said first and second clock signals; in response to said counter reaching a specified value, restarting said first and second clock signals; and adjusting said second frequency in response to said change in frequency, wherein said second clock signal is individually adjustable without an adjustment to said third clock signal. - View Dependent Claims (17, 18, 19, 20, 21, 22, 27)
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23. A system comprising:
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means for monitoring operating conditions of a processing unit; means for generating a clock signal at a frequency; and means for adjusting said clock signal to provide clock signals at different frequencies to said processing unit and to a second component concurrently and for individually adjusting said different frequencies;
wherein, in response to initiation of a change in frequency for said processing unit, a means for counting is started and clock signals to said processing unit and said second component are stopped; and
wherein further, in response to said means for counting reaching a specified value, said clock signals to said processing unit and said second component are started. - View Dependent Claims (24, 26)
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Specification
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Litigation Data
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Current AssigneeSemcon IP Inc. (Quest Patent Research Corporation)
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Original AssigneeIntellectual Ventures Funding LLC (Intellectual Ventures LLC)
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InventorsKlayman, Keith, Read, Andrew, Lawrence, Thomas, Halepete, Sameer, Anvin, H. Peter, Chen, Zongjian, D'Souza, Godfrey P., Fleischmann, Marc
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Primary Examiner(s)Myers, Paul R
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Application NumberUS12/502,685Publication NumberTime in Patent Office1,561 DaysField of Search713/322, 713/501, 331/17, 331/179US Class Current713/322CPC Class CodesG06F 1/08 Clock generators with chang...G06F 1/3203 Power management, i.e. even...G06F 1/324 by lowering clock frequencyG06F 1/3296 by lowering the supply or o...Y02D 10/00 Energy efficient computing,...
