Architecture for a sea of platforms
DC
First Claim
Patent Images
1. A system for providing distributed dynamic functionality in an electronic environment comprising:
- a plurality of platforms, the platforms suitable for providing a logic function, the platforms including embedded programmable logic, memory and a reconfigurable core, the logic, memory and reconfigurable core communicatively coupled via a fabric interconnect; and
a map expressing logic functions of the plurality of platforms;
wherein the reconfigurable core is configured as a base processor design plus instruction set extensions designed to carry out function-specific logical and arithmetic operations.
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Abstract
The present invention is directed to platform architecture. A system for providing distributed dynamic functionality in an electronic environment may include a plurality of platforms. The platforms are suitable for providing a logic function, and include embedded programmable logic, memory and a reconfigurable core. The logic, memory and reconfigurable core are communicatively coupled via a fabric interconnect. A map is also included which expresses logic functions of the plurality of platforms.
12 Citations
6 Claims
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1. A system for providing distributed dynamic functionality in an electronic environment comprising:
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a plurality of platforms, the platforms suitable for providing a logic function, the platforms including embedded programmable logic, memory and a reconfigurable core, the logic, memory and reconfigurable core communicatively coupled via a fabric interconnect; and
a map expressing logic functions of the plurality of platforms;
wherein the reconfigurable core is configured as a base processor design plus instruction set extensions designed to carry out function-specific logical and arithmetic operations.
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2. A system for providing distributed dynamic functionality in an electronic environment comprising:
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a plurality of platforms, the platforms suitable for providing a logic function, the platforms including embedded programmable logic, memory and a reconfigurable core, the logic, memory and reconfigurable core communicatively coupled via a fabric interconnect; and
a map expressing logic functions of the plurality of platforms;
wherein the fabric interconnect is realized within a switching fabric which permits adaptive interconnect and access paths to be defined on the fly.
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3. A system for providing distributed dynamic functionality in an electronic environment comprising:
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a plurality of platforms, the platforms suitable for providing a logic function, the platforms including embedded programmable logic, memory and a reconfigurable core, the logic, memory and reconfigurable core communicatively coupled via a fabric interconnect; and
a map expressing logic functions of the plurality of platforms;
wherein instruction set extensions are utilized through the use of the map to coordinate discrete instruction set extensions on a cycle-by-cycle basis and execution is synchronized across the plurality of platforms utilizing an isochronous fabric interconnect so that the instruction set extensions are utilized by corresponding platforms at a corresponding cycle, and wherein logic functions are targeted at the platforms indicated by the map as having corresponding functionality at a corresponding point in time.
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4. A system for providing distributed dynamic functionality in an electronic environment comprising:
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a plurality of platforms communicatively coupled via an isochronous fabric, the platforms suitable for providing a logic function, the platforms including embedded programmable logic, memory and a reconfigurable core communicatively coupled; and
a map expressing availability of the plurality of platforms for performing a logic function;
wherein the reconfigurable core is configured as a base processor design plus instruction set extensions designed to carry out function-specific logical and arithmetic operations.
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5. A system for providing distributed dynamic functionality in an electronic environment comprising:
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a plurality of platforms communicatively coupled via an isochronous fabric, the platforms suitable for providing a logic function, the platforms including embedded programmable logic, memory and a reconfigurable core communicatively coupled; and
a map expressing availability of the plurality of platforms for performing a logic function;
wherein the isochronous fabric is realized within a switching fabric which permits adaptive interconnect and access paths to be defined on the fly.
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6. A system for providing distributed dynamic functionality in an electronic environment comprising:
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a plurality of platforms communicatively coupled via an isochronous fabric, the platforms suitable for providing a logic function, the platforms including embedded programmable logic, memory and a reconfigurable core communicatively coupled; and
a map expressing availability of the plurality of platforms for performing a logic function;
wherein instruction set extensions are utilized through the use of the map to coordinate discrete instruction set extensions on a cycle-by-cycle basis and execution is synchronized across the plurality of platforms utilizing an isochronous fabric interconnect so that the instruction set extensions are utilized by corresponding platforms at a corresponding cycle, and wherein logic functions are targeted at the platforms indicated by the map as having corresponding functionality at a corresponding point in time.
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Specification
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Litigation Data
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Current AssigneeBell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
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Original AssigneeLSI Logic Corporation (Broadcom, Inc.)
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InventorsHamlin, Christopher L.
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Primary Examiner(s)Siek, Vuthe
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Assistant Examiner(s)LEVIN, NAUM B
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Application NumberUS10/044,781Publication NumberTime in Patent Office656 DaysField of Search716/16-18, 370/254, 370/352, 370/392, 370/395.1, 370/397, 370/398, 365/49, 326/86US Class Current326/38CPC Class CodesG06F 30/30 Circuit designG06F 30/34 for reconfigurable circuits...G06F 30/343 Logical level
