Clock data recovery circuitry associated with programmable logic device circuitry

US 7,227,918 B2
Filed: 03/13/2001
Issued: 06/05/2007
Est. Priority Date: 03/14/2000
Status: Expired due to Term

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1. Apparatus for receiving and processing a CDR signal comprising:

PLD circuitry;

first input circuitry configured to receive the CDR signal, wherein the CDR signal includes data information and a clock signal embedded in a serial data stream;

second input circuitry configured to receive an external reference clock signal, wherein the external reference clock signal has a frequency related to a frequency of the embedded clock signal; and

processing circuitry at least partly controlled by the PLD circuitry and configured to use the external reference clock signal to recover the data information from the CDR signal.

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Abstract

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.

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138 Claims

1. Apparatus for receiving and processing a CDR signal comprising:
- PLD circuitry;
  
  first input circuitry configured to receive the CDR signal, wherein the CDR signal includes data information and a clock signal embedded in a serial data stream;
  
  second input circuitry configured to receive an external reference clock signal, wherein the external reference clock signal has a frequency related to a frequency of the embedded clock signal; and
  
  processing circuitry at least partly controlled by the PLD circuitry and configured to use the external reference clock signal to recover the data information from the CDR signal.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
- - 2. The apparatus defined in claim 1 wherein the PLD circuitry, the first and second input circuitries, and the processing circuitry are all integrated in a single integrated circuit device.
  - 3. The apparatus defined in claim 1 wherein the first input circuitry comprises:
    - phase locked loop circuitry.
  - 4. The apparatus defined in claim 3 wherein the phase locked loop circuitry is programmable with respect to an operating parameter.
  - 5. The apparatus defined in claim 3 wherein the phase locked loop circuitry is configured to power down in response to a programmable power down signal.
  - 6. The apparatus defined in claim 1 wherein the second input circuitry comprises:
    - phase locked loop circuitry.
  - 7. The apparatus defined in claim 6 wherein the phase locked loop circuitry is programmable with respect to an operating parameter.
  - 8. The apparatus defined in claim 6 wherein the phase locked loop circuitry is configured to power down in response to a programmable power down signal.
  - 9. The apparatus defined in claim 6 wherein the first input circuitry comprises:
    - further phase locked loop circuitry configured to receive an output signal of the phase locked loop circuitry and to produce a recovered clock signal that is synchronized with the CDR signal.
  - 10. The apparatus defined in claim 9 wherein the further phase locked loop circuitry is further configured to adjust the phase of the output signal of the phase locked loop circuitry to produce the recovered clock signal.
  - 11. The apparatus defined in claim 1 wherein the processing circuitry comprises:
    - deserializer circuitry configured to convert the data information from serial to parallel form.
  - 12. The apparatus defined in claim 11 wherein the deserializer circuitry is programmable with respect to an operating parameter.
  - 13. The apparatus defined in claim 11 wherein the deserializer circuitry is further configured to reset in response to a reset signal selectively produced by the PLD circuitry.
  - 14. The apparatus defined in claim 1 wherein the processing circuitry comprises:
    - buffer circuitry configured to buffer the data information between a clock regime associated with reference clock signal and a different clock regime.
  - 15. The apparatus defined in claim 14 wherein the buffer circuitry is further configured to reset in response to a reset signal selectively produced by the PLD circuitry.
  - 16. The apparatus defined in claim 1 wherein at least one of the first input, second input and processing circuitries is configured to apply to the PLD circuitry a condition-monitoring signal indicative of an operating condition of that at least one circuitry.
  - 17. The apparatus defined in claim 1 wherein at least one of the first input, second input, and processing circuitries includes a component that is reset by a reset signal selectively produced by the PLD circuitry.
  - 18. The apparatus defined in claim 1 wherein the first input circuitry is further configured for alternate use to receive a non-CDR data signal;
    - the second input circuitry is further configured for alternate use to receive a non-CDR clock signal that is synchronized with the non-CDR data signal; and
      
      the processing circuitry is further configured for alternate use to derive the data information from the non-CDR data signal using the non-CDR clock signal.
  - 19. The apparatus defined in claim 18 wherein the non-CDR data signal is an LVDS signal.
  - 20. The apparatus defined in claim 1 further comprising:
    - output circuitry configured to receive further data information from the PLD circuitry and to use the reference clock signal to encode the further data information as a further CDR signal for output by the apparatus.
  - 21. The apparatus defined in claim 20 further comprising:
    - loopback circuitry configured to selectively use the further CDR signal as the CDR signal.
  - 22. The apparatus defined in claim 21 wherein the loopback circuitry is configured so that it can be controlled by a signal from the PLD circuitry.
  - 23. The apparatus defined in claim 20 further comprising:
    - loopback circuitry configured to selectively route the CDR signal for output by the apparatus in lieu of the further CDR signal.
  - 24. The apparatus defined in claim 23 wherein the loopback circuitry is configured so that it can be controlled by a signal from the PLD circuitry.
  - 25. The circuitry defined in claim 21 wherein the loopback circuitry is further configured for selective control by the PLD circuitry.

26. Apparatus for producing and transmitting a CDR signal comprising:
- PLD circuitry configured to produce data information and a PLD clock signal;
  
  input circuitry configured to receive an external reference clock signal;
  
  buffer circuitry configured to buffer the data information between a clock regime associated with the PLD clock signal and a different clock regime associated with the external reference clock signal, wherein the clock regimes have different frequencies; and
  
  output circuitry configured to use the reference clock signal to produce the CDR signal including the data information and an embedded clock signal having a frequency related to the external reference clock signal.
- View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
- - 27. The apparatus defined in claim 26 wherein the PLD circuitry, the input circuitry, and the output circuitry are all integrated in a single integrated circuit device.
  - 28. The apparatus defined in claim 26 wherein the input circuitry comprises:
    - phase locked loop circuitry.
  - 29. The apparatus defined in claim 28 wherein the phase locked loop circuitry is programmable with respect to an operating parameter.
  - 30. The apparatus defined in claim 28 wherein the phase locked loop circuitry is configured to power down in response to a programmable power down signal.
  - 31. The apparatus defined in claim 26 wherein the output circuitry comprises:
    - serializer circuitry configured to convert the data information from parallel to serial form.
  - 32. The apparatus defined in claim 31 wherein the serializer circuitry is programmable with respect to an operating parameter.
  - 33. The apparatus defined in claim 26 wherein at least one of the input and output circuitries is configured to apply to the PLD circuitry a condition-monitoring signal indicative of an operating condition of that at least one circuitry.
  - 34. The apparatus defined in claim 26 wherein at least one of the input and output circuitries includes a component that is reset by a reset signal selectively produced by the PLD circuitry.
  - 35. The apparatus defined in claim 26 wherein the PLD circuitry is further configured to produce a non-CDR clock signal synchronized with the data information, and wherein the output circuitry is further configured for alternative use in outputting the data information in non-CDR form in parallel with the non-CDR clock signal.
  - 36. The apparatus defined in claim 35 wherein the output circuitry is further configured to selectively frequency-scale the non-CDR clock signal by a predetermined scale factor prior to outputting the non-CDR clock signal in frequency-scaled form.
  - 37. The apparatus defined in claim 36 wherein the output circuitry is programmable with respect to the scale factor.
  - 38. The apparatus defined in claim 35 wherein the non-CDR form of the data information is an LVDS signal.

39. Apparatus for receiving an information signal which includes data information having clock information for the data information embedded in the data information comprising:
- first input circuitry configured to receive the information signal;
  
  circuitry configured to receive a programmable scale factor;
  
  second input circuitry configured to receive an external reference clock signal having a reference frequency which is related to a frequency of the clock information by the programmable scale factor;
  
  reference clock signal processing circuitry configured to use the information signal and the reference clock signal to produce a recovered clock signal having phase and frequency which respectively correspond to a phase and a frequency of the clock information; and
  
  data recovery circuitry configured to use the recovered clock signal and the information signal to produce a data output signal indicative of the data information in the information signal.
- View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68)
- - 40. The apparatus defined in claim 39 further comprising:
    - deserializer circuitry configured to convert the data output signal to a plurality of parallel data subsignals, each of which represents a respective portion of the data information indicated by the data output signal.
  - 41. The apparatus defined in claim 40 wherein the deserializer circuitry is programmable with respect to how many parallel data subsignals are produced.
  - 42. The apparatus defined in claim 39 further comprising:
    - synchronizer circuitry configured to convert the data output signal to a further data output signal synchronized with a read control signal which can have phase and frequency substantially unrelated to the phase and frequency of the reference clock signal and the recovered clock signal.
  - 43. The apparatus defined in claim 42 further comprising:
    - selection circuitry configured to select as a final data output signal either the data output signal or the further data output signal.
  - 44. The apparatus defined in claim 39 wherein the reference clock signal processing circuitry is further configured to use the scale factor in producing the recovered clock signal.
  - 45. The apparatus defined in claim 44 wherein the reference clock signal processing circuitry is programmable with respect to the scale factor.
  - 46. The apparatus defined in claim 39 wherein the information signal is applied to the first input circuitry as a pair of differential signals, and wherein the first input circuitry comprises differential driver circuitry configured to use the differential signals to produce a single output signal for further processing by the apparatus.
  - 47. The apparatus defined in claim 39 wherein the reference clock signal is applied to the second input circuitry as a pair of differential signals, and wherein the second input circuitry comprises differential driver circuitry configured to use the differential signals to produce a single output signal for further processing by the apparatus.
  - 48. The apparatus defined in claim 39 wherein the reference clock signal processing circuitry comprises:
    - phase locked loop circuitry configured to use the reference clock signal and the scale factor to produce a plurality of candidate further reference clock signals, each having the frequency of the clock information and having a phase which is different from the phases of all the other candidate further reference clock signals.
  - 49. The apparatus defined in claim 48 wherein the reference clock signal processing circuitry further comprises:
    - further phase locked loop circuitry configured to use the information signal and the candidate further reference clock signals to produce the recovered clock signal.
  - 50. The apparatus defined in claim 49 wherein the further phase locked loop circuitry comprises:
    - selection circuitry configured to select as the recovered clock signal the one of the candidate reference clock signals having the phase that works best with the phase of the clock information.
  - 51. The apparatus defined in claim 39 wherein the data recovery circuitry comprises:
    - register circuitry having a data input terminal to which the information signal is applied and a clock input terminal to which the recovered clock signal is applied, the register circuitry being configured to store and output samples of the signal applied to the data input terminal in synchronism with the signal applied to the clock input terminal.
  - 52. The apparatus defined in claim 51 wherein the data recovery circuitry further comprises:
    - buffer memory circuitry configured to store multiple successive signal samples output by the register in synchronism with the recovered clock signal and to output those samples in the same order in response to another separate read clock signal.
  - 53. The apparatus defined in claim 39 wherein the information signal represents successive words of J serial bits of data, and wherein the data recovery circuitry comprises:
    - shift register circuitry having a plurality of serially connected stages and configured to shift in successive samples of the information signal in synchronism with the recovered clock signal;
      
      frequency divider circuitry configured to divide the recovered clock signal by J to produce a further reference clock signal; and
      
      unload circuitry configured to unload all stages of the shift register circuitry in parallel word form in synchronism with the further reference clock signal.
  - 54. The apparatus defined in claim 53 wherein the frequency divider circuitry is programmable with respect to J.
  - 55. The apparatus defined in claim 53 wherein the data recovery circuitry further comprises:
    - buffer memory circuitry configured to store multiple successive parallel words from the unload circuitry in synchronism with the still further reference clock signal and to output those parallel words in a same order in response to another separate read clock signal.
  - 56. The apparatus defined in claim 39 further comprising:
    - PLD circuitry configured to use the data output signal.
  - 57. The apparatus defined in claim 56 wherein all of the circuitries are disposed on a single integrated circuit.
  - 58. The apparatus defined in claim 56 further comprising:
    - routing circuitry configured to selectively apply a signal indicative of the recovered clock signal to the PLD circuitry.
  - 59. The apparatus defined in claim 42 further comprising:
    - PLD circuitry configured to produce the read control signal.
  - 60. The apparatus defined in claim 59 wherein the PLD circuitry is further configured to use the data output signal.
  - 61. A signaling system comprising:
    - the apparatus defined in claim 39;
      
      a first source of the information signal;
      
      a second source of the reference clock signal;
      
      a first connection between the first source and the first input circuitry; and
      
      a second connection between the second source and the second input circuitry.
  - 62. The system defined in claim 61 wherein the first and second input circuitries are disposed on a common integrated circuit which does not also include the first and second sources.
  - 63. The apparatus defined in claim 39 wherein the information signal is a clock data recovery signal.
  - 64. The apparatus defined in claim 39 further comprising:
    - alternative reference clock signal processing circuitry configured to selectively alternatively produce a further reference clock signal based on the reference clock signal and without regard for the information signal.
  - 65. A digital processing system comprising:
    - processing circuitry;
      
      a memory coupled to said processing circuitry; and
      
      apparatus as defined in claim 39 coupled to the processing circuitry and the memory.
  - 66. A printed circuit board on which is mounted apparatus as defined in claim 39.
  - 67. The printed circuit board defined in claim 66 further comprising:
    - a memory mounted on the printed circuit board and coupled to the apparatus.
  - 68. The printed circuit board defined in claim 66 further comprising:
    - processing circuitry mounted on the printed circuit board and coupled to the apparatus.

69. Apparatus for transmitting an information signal which includes data information having clock information for the data information embedded in the data information comprising:
- circuitry configured to receive a programmable scale factor;
  
  input circuitry configured to receive an external reference clock signal having a reference frequency which is related to a frequency of the clock information by the programmable scale factor;
  
  reference clock signal processing circuitry configured to use the external reference clock signal to produce a further reference clock signal having the frequency of the clock information;
  
  data source circuitry configured to produce a data signal indicative of the data information; and
  
  data signal processing circuitry configured to process the data signal in accordance with the further reference clock signal to produce the information signal.
- View Dependent Claims (70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98)
- - 70. The apparatus defined in claim 69 wherein the data source circuitry is configured to produce the data signal as a plurality of parallel data subsignals, each of which represents a respective portion of the data information, and wherein the data signal processing circuitry comprises:
    - serializer circuitry configured to convert the plurality of parallel data subsignals to a single serial data signal.
  - 71. The apparatus defined in claim 70 wherein the serializer circuitry is programmable with respect to how many parallel data subsignals are converted.
  - 72. The apparatus defined in claim 69 wherein the data signal processing circuitry comprises:
    - synchronizer circuitry configured to receive the data signal in synchronism with a write control signal and to subsequently output the data signal in synchronism with the further reference clock signal, wherein the write control signal can have phase and frequency which are substantially unrelated to the phase and frequency of the reference clock signal and the further reference clock signal.
  - 73. The apparatus defined in claim 72 wherein the data signal processing circuitry further comprises:
    - selection circuitry configured to allow the data signal to selectively bypass the synchronizer circuitry.
  - 74. The apparatus defined in claim 69 wherein the reference clock signal processing circuitry is further configured to use the scale factor in producing the further reference clock signal.
  - 75. The apparatus defined in claim 74 wherein the reference clock signal processing circuitry is programmable with respect to the scale factor.
  - 76. The apparatus defined in claim 69 wherein the reference clock signal is applied to the input circuitry as a pair of differential signals, and wherein the input circuitry comprises differential driver circuitry configured to use the differential signals to produce a single output signal for further processing by the apparatus.
  - 77. The apparatus defined in claim 69 wherein the data signal processing circuitry comprises differential driver circuitry configured to transmit the information signal as a pair of differential signals.
  - 78. The apparatus defined in claim 69 wherein the reference clock signal processing circuitry comprises:
    - phase locked loop circuitry configured to use the reference clock signal and the scale factor to produce the further reference clock signal.
  - 79. The apparatus defined in claim 69 wherein the data signal processing circuitry comprises:
    - register circuitry having a data input terminal to which the data signal is applied and a clock input terminal to which the further reference clock signal is applied, the register circuitry being configured to store samples of the signal applied to the data input terminal and to output those samples in synchronism with the signal applied to the clock input terminal.
  - 80. The apparatus defined in claim 69 wherein the data signal comprises a plurality of parallel data subsignals, each of which is indicative of a portion of the data information, and wherein the data signal processing circuitry comprises:
    - register circuitry having a plurality of data input terminals to which the data subsignals are respectively applied and a clock input terminal to which the further reference clock signal is applied, the register circuitry being configured to store samples of the signals applied to the data input terminals and to output those samples in series in synchronism with the signal applied to the clock input terminal.
  - 81. The apparatus defined in claim 80 wherein the data signal processing circuitry further comprises:
    - buffer memory circuitry configured to store multiple successive samples of each of the data subsignals in response to another separate write clock signal and to output those samples in the same order in synchronism with the further reference clock signal.
  - 82. The apparatus defined in claim 80 wherein the plurality of parallel data subsignals comprises J parallel data subsignals, and wherein the register circuitry comprises:
    - shift register circuitry having a plurality of serially connected stages and configured to shift out contents of those stages in series in synchronism with the further reference clock signal;
      
      frequency divider circuitry configured to divide the further reference clock signal by J to produce a still further reference clock signal; and
      
      load circuitry configured to load, in parallel, all stages of the shift register circuitry with samples of the data subsignals in synchronism with the still further reference clock signal.
  - 83. The apparatus defined in claim 82 wherein the frequency divider circuitry is programmable with respect to J.
  - 84. The apparatus defined in claim 82 wherein the register circuitry further comprises:
    - buffer memory circuitry configured to store multiple successive parallel words of samples of the data subsignals in response to another separate write clock signal and to output those parallel words in a same order in response to the still further reference clock signal.
  - 85. The apparatus defined in claim 69 wherein the data source circuitry comprises PLD circuitry.
  - 86. The apparatus defined in claim 85 wherein all of the circuitries are disposed on a single integrated circuit.
  - 87. The apparatus defined in claim 85 further comprising:
    - routing circuitry configured to selectively apply a signal indicative of the further reference clock signal to the PLD circuitry.
  - 88. The apparatus defined in claim 72 further comprising:
    - PLD circuitry configured to produce the write control signal.
  - 89. The apparatus defined in claim 88 wherein the PLD circuitry is further configured to include the data source circuitry.
  - 90. A signaling system comprising:
    - the apparatus defined in claim 69;
      
      a first source of the reference clock signal;
      
      a second receiver of the information signal;
      
      a first connection between the first source and the input circuitry; and
      
      a second connection between the data signal processing circuitry and the second receiver.
  - 91. The system defined in claim 90 wherein the input circuitry and the data signal processing circuitry are disposed on a common integrated circuit which does not also include the first source and the second receiver.
  - 92. The apparatus defined in claim 69 wherein the information signal is a clock data recovery signal.
  - 93. The apparatus defined in claim 69 further comprising:
    - alternative reference clock signal source circuitry configured to produce an alternative clock signal;
      
      signal selection circuitry configured to allow the alternative clock signal to be alternatively selectively used by the data processing circuitry as the further reference clock signal; and
      
      output circuitry configured to output the alternative clock signal in parallel with the information signal.
  - 94. The apparatus defined in claim 93 wherein the data signal processing circuitry comprises first differential driver circuitry configured to transmit the information signal as a first pair of differential signals, and wherein the output circuitry comprises second differential driver circuitry configured to transmit the alternative clock signal as a second pair of differential signals.
  - 95. A digital processing system comprising:
    - processing circuitry;
      
      a memory coupled to said processing circuitry; and
      
      apparatus as defined in claim 69 coupled to the processing circuitry and the memory.
  - 96. A printed circuit board on which is mounted apparatus as defined in claim 69.
  - 97. The printed circuit board defined in claim 96 further comprising:
    - a memory mounted on the printed circuit board and coupled to the apparatus.
  - 98. The printed circuit board defined in claim 96 further comprising:
    - processing circuitry mounted on the printed circuit board and coupled to the apparatus.

99. Programmable serializer circuitry comprising:
- control circuitry that receives a programmable number;
  
  input circuitry that receives the programmable number of input signals in parallel; and
  
  output circuitry that produces an output signal that is serially indicative of the programmable number input signals one after another.
- View Dependent Claims (100, 101, 102, 103, 104, 105, 106, 107, 108)
- - 100. The programmable serializer circuitry defined in claim 99 wherein the output signal is synchronized with a first clock signal having a first clock rate, and wherein the circuitry further comprises:
    - clock rate divider circuitry that divides the clock rate by a programmable factor to produce a second clock signal for timing passage of information indicative of the input signals in parallel from the input circuitry to the output circuitry.
  - 101. The programmable serializer circuitry defined in claim 100 wherein the factor is programmable to equal the programmable number.
  - 102. The programmable serializer circuitry defined in claim 99 wherein the input circuitry comprises a predetermined plural quantity of register stages, and wherein the number is programmable to any integer value up to and including the plural quantity.
  - 103. The programmable serializer circuitry defined in claim 102 wherein the register stages store the input signals in parallel.
  - 104. The programmable serializer circuitry defined in claim 103 wherein the register stages further output in parallel to the output circuitry information indicative of the input signals.
  - 105. The programmable serializer circuitry defined in claim 99 wherein the output circuitry comprises a predetermined plural quantity of register stages, and wherein the number is programmable to any integer value up to and including the plural quantity.
  - 106. The programmable serializer circuitry defined in claim 105 wherein the register stages store in parallel information from the input circuitry indicative of the input signals.
  - 107. The programmable serializer circuitry defined in claim 106 wherein the output circuitry further outputs information from the registers in a predetermined series one after another.
  - 108. A programmable system comprising:
    - programmable serializer circuitry as defined in claim 99; and
      
      programmable logic circuitry for supplying the input signals.

109. Programmable deserializer circuitry comprising:
- control circuitry that receives a programmable number;
  
  input circuitry that receives an input signal serially indicative of plural bits of information one after another and stores the programmable number of successive ones of those bits; and
  
  output circuitry that produces the programmable number of output signals in parallel, each of the output signals being indicative of a respective one of the bits stored by the input circuitry.
- View Dependent Claims (110, 111, 112, 113, 114, 115, 116, 117, 118)
- - 110. The programmable deserializer circuitry defined in claim 109 wherein the input signal is synchronized with a first clock signal having a first clock rate, and wherein the circuitry further comprises:
    - clock rate divider circuitry that divides the clock rate by a programmable factor to produce a second clock signal for timing the passage of information indicative of the bits stored by the input circuitry in parallel from the input circuitry to the output circuitry.
  - 111. The programmable deserializer circuitry defined in claim 110 wherein the factor is programmable to equal the programmable number.
  - 112. The programmable deserializer circuitry defined in claim 109 wherein the input circuitry comprises a predetermined plural quantity of register stages, and wherein the number is programmable to any integer value up to and including the plural quantity.
  - 113. The programmable deserializer circuitry defined in claim 112 wherein each of the register stages stores one of the bits.
  - 114. The programmable deserializer circuitry defined in claim 113 wherein the register stages further output in parallel to the output circuitry information indicative of the bits stored in the register stages.
  - 115. The programmable deserializer circuitry defined in claim 109 wherein the output circuitry comprises a predetermined plural quantity of register stages, and wherein the number is programmable to any integer value up to and including the plural quantity.
  - 116. The programmable deserializer circuitry defined in claim 115 wherein the register stages store in parallel information from the input circuitry indicative of the bits stored by the input circuitry.
  - 117. The programmable deserializer circuitry defined in claim 116 wherein the output circuitry further outputs information from the registers in parallel.
  - 118. A programmable system comprising:
    - programmable deserializer circuitry as defined in claim 109; and
      
      programmable logic circuitry for receiving the output signals.

119. Apparatus for receiving and processing a plurality of CDR signals, each of which includes data information and clock information, comprising:
- first circuitry producing a plurality of candidate recovered clock signals from a reference clock signal, the candidate recovered clock signals having phases that are shifted relative to one another; and
  
  a plurality of second circuitries, each receiving a respective one of the CDR signals and using the candidate reference clock signals to recover the clock information from the CDR signal received by that second circuitry.
- View Dependent Claims (120, 121, 122, 123, 124)
- - 120. The apparatus defined in claim 119 wherein the clock information of all of the CDR signals has a predetermined common frequency.
  - 121. The apparatus defined in claim 120 wherein the reference clock signal has frequency having a predetermined relationship to the predetermined common frequency.
  - 122. The apparatus defined in claim 121 wherein the first circuitry comprises phase locked loop circuitry.
  - 123. The apparatus defined in claim 121 wherein each of the second circuitries comprises:
    - selection circuitry that selects at least one of the candidate recovered clock signals that is close in phase to the clock information in the CDR signal received by that second circuitry.
  - 124. The apparatus defined in claim 121 wherein each of the second circuitries comprises:
    - selection circuitry that selects one of the candidate recovered clock signals that is closest in phase to the clock information in the CDR signal received by that second circuitry.

125. Apparatus for receiving and processing a CDR signal comprising:
- first input circuitry operative to receive the CDR signal, wherein the CDR signal includes data information and a clock signal embedded in a serial data stream;
  
  second input circuitry operative to receive a reference clock signal, wherein the reference clock signal has a frequency related to a frequency of the embedded clock signal;
  
  phase locked loop circuitry operative to use the reference clock signal to generate a recovered clock signal having a frequency equal to the frequency of the embedded clock signal; and
  
  processing circuitry operative to use the recovered clock signal to recover the data information from the CDR signal.
- View Dependent Claims (126, 127, 128, 129, 130, 131, 132, 133)
- - 126. The apparatus defined in claim 125 wherein the first input circuitry, the second input circuitry, the phase locked loop circuitry, and the processing circuitry are all integrated in a single integrated circuit device that includes PLD circuitry.
  - 127. The apparatus defined in claim 125 wherein the phase locked loop circuitry is programmable with respect to an operating parameter.
  - 128. The apparatus defined in claim 125 wherein the frequency of the reference clock signal is related to the frequency of the embedded clock signal by a scale factor.
  - 129. The apparatus defined in claim 125 wherein the phase locked loop circuitry is further operative to adjust the phase of the output signal of the phase locked loop circuitry to produce the recovered clock signal.
  - 130. The apparatus defined in claim 125 wherein the processing circuitry comprises:
    - deserializer circuitry operative to convert the data information from serial to parallel form.
  - 131. The apparatus defined in claim 125 further comprising:
    - output circuitry operative to receive further data information and to use the reference clock signal to encode the further data information as a further CDR signal for output by the apparatus.
  - 132. The apparatus defined in claim 131 further comprising:
    - loopback circuitry operative to selectively use the further CDR signal as the CDR signal.
  - 133. The apparatus defined in claim 131 further comprising:
    - loopback circuitry operative to selectively route the CDR signal for output by the apparatus in lieu of the further CDR signal.

134. Apparatus for producing and transmitting a CDR signal comprising:
- first input circuitry operative to receive a reference clock signal;
  
  second input circuitry operative to receive a data information signal;
  
  phase locked loop circuitry operative to use the reference clock signal to generate an embedded clock signal;
  
  buffer circuitry operative to buffer the data information between a clock regime associated with the data information and a clock regime associated with the embedded clock signal, wherein the clock regimes have different frequencies; and
  
  output circuitry operative to use the embedded clock signal to produce the CDR signal from the data information signal.
- View Dependent Claims (135, 136, 137, 138)
- - 135. The apparatus defined in claim 134 wherein the first input circuitry, the second input circuitry, the phase locked loop circuitry, the buffer circuitry, and the output circuitry are all integrated in a single integrated circuit device that includes PLD circuitry.
  - 136. The apparatus defined in claim 134 wherein the phase locked loop circuitry is programmable with respect to an operating parameter.
  - 137. The apparatus defined in claim 134 wherein the frequency of the reference clock signal is related to the frequency of the embedded clock signal by a scale factor.
  - 138. The apparatus defined in claim 134 wherein the output circuitry comprises:
    - serializer circuitry operative to convert the data information from parallel to serial form.

Specification

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Litigation Campaign Assessment

Litigation Data

Current Assignee
Altera Corporation (Intel Corporation)
Original Assignee
Altera Corporation (Intel Corporation)
Inventors
Lee, Chong, Patel, Rakesh, Turner, John, Butler, Paul, Lui, Henry, Aung, Edward
Primary Examiner(s)
Bayard; Emmanuel

Application Number

US09/805,843
Publication Number

US 20010033188A1
Time in Patent Office

2,275 Days
Field of Search

375/215, 375/368, 375/371, 375/372, 375/373, 375/356, 375/354, 375/355, 375/358, 375/376, 375/211, 375/213, 375/214, 700/9, 700/48, 341/100, 341/101, 716/6, 370/516, 370/503
US Class Current

375/355
CPC Class Codes

G11C 7/22   Read-write [R-W] timing or ...

G11C 7/222   Clock generating, synchroni...

H03K 19/17732   Macroblocks

H03K 19/17744   for input/output signals

H03L 7/07   using several loops, e.g. f...

H03L 7/0802   the loop being adapted for ...

H03L 7/0814   the phase shifting device b...

H03L 7/089   the phase or frequency dete...

H03L 7/0891   the up-down pulses controll...

H03L 7/0995   the oscillator comprising a...

H03L 7/187   using means for coarse tuni...

H03L 7/199   with reset of the frequency...

H03M 9/00   Parallel/series conversion ...

H04L 7/0025   interpolation of clock signal

H04L 7/02   Speed or phase control by t...

H04L 7/0337   Selecting between two or mo...

Clock data recovery circuitry associated with programmable logic device circuitry

First Claim

1 Assignment

Litigations

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Accused Products

Abstract

118 Citations

138 Claims

Specification

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Clock data recovery circuitry associated with programmable logic device circuitry

First Claim

1 Assignment

Subscription Required

Subscription Required

Litigations

0 Petitions

Subscription Required

Accused Products

Subscription Required

Abstract

118 Citations

138 Claims

Specification

Subscription Required

Solutions

Use Cases

Quick Links