Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults
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Abstract
A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.
21 Citations
82 Claims
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1-75. -75. (canceled)
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76. A computer-aided design (CAD) method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test and self-test mode, where N>
- 1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a selected number of shift clock pulses and a selected number of capture clock pulses, each shift clock pulse comprising a clock pulse applied in scan mode, each capture clock pulse comprising a clock pulse applied in normal mode, said CAD method comprising the computer-implemented steps of;
(a) compiling the HDL code or netlist that represents said integrated circuit or circuit assembly in physical form into a design database;
(b) performing test rule check for checking whether said design database contains any multiple-capture rule violations in said scan-test or said self-test mode;
(c) performing test rule repair until all said multiple-capture rule violations have been fixed;
(d) performing multiple-capture test synthesis for generating a testable HDL code or netlist; and
(e) generating HDL test benches and automatic test equipment (ATE) test programs for verifying the correctness of said testable HDL netlist in said scan-test or said self-test mode. - View Dependent Claims (77, 78, 79, 80, 81, 82)
- 1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a selected number of shift clock pulses and a selected number of capture clock pulses, each shift clock pulse comprising a clock pulse applied in scan mode, each capture clock pulse comprising a clock pulse applied in normal mode, said CAD method comprising the computer-implemented steps of;
Specification
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- Resources
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Current AssigneeSyntest Technologies Incorporated
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Original AssigneeSyntest Technologies Incorporated
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InventorsWang, Laung-Terng, Wen, Xiaoqing, Hsu, Po-Ching
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current714/726
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CPC Class CodesG01R 31/31704 Design for test; Design ver...G01R 31/318552 Clock circuits detailsG01R 31/318594 Timing aspects clock circui...G06F 30/327 Logic synthesis; Behaviour ...G06F 30/33 Design verification, e.g. f...G06F 30/3308 using simulationG06F 30/3312 Timing analysis
