Exchanging data between memory controllers
First Claim
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1. A device for exchanging data, comprising:
- a plurality of memory controllers, wherein each memory controller of said plurality of memory controllers is coupled to an allocated memory for storing data; and
an interconnect for connecting said plurality of memory controllers,wherein each memory controller of said plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over said interconnect, wherein each accelerator of said plurality of accelerators is configured to carry out a plurality of concurrent deterministic operations for at least one of;
marking phases of garbage collection in said allocated memory, copying data stored in said allocated memory, replicating data structures stored in said allocated memory, filling memory blocks in said allocated memory, and erasing memory blocks in said allocated memory; and
wherein each accelerator of said plurality of accelerators has a set of registers for carrying out said concurrent deterministic operations.
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Abstract
A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect.
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Citations
13 Claims
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1. A device for exchanging data, comprising:
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a plurality of memory controllers, wherein each memory controller of said plurality of memory controllers is coupled to an allocated memory for storing data; and an interconnect for connecting said plurality of memory controllers, wherein each memory controller of said plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over said interconnect, wherein each accelerator of said plurality of accelerators is configured to carry out a plurality of concurrent deterministic operations for at least one of;
marking phases of garbage collection in said allocated memory, copying data stored in said allocated memory, replicating data structures stored in said allocated memory, filling memory blocks in said allocated memory, and erasing memory blocks in said allocated memory; and
wherein each accelerator of said plurality of accelerators has a set of registers for carrying out said concurrent deterministic operations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification